• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.8
• /
• pp.54-60
• /
• 2008

The bus architecture consists of a master initiating a communication transaction, a slave responding to the transaction, a arbiter selecting a master, a bridge connecting buses and so on. Recently this is more complicated and developed toward multi-bus architecture. In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory selector is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• Journal of the Korea Society of Computer and Information
• /
• v.10 no.5 s.37
• /
• pp.313-322
• /
• 2005

In this paper, we implement and verify performance monitor for parallel signal processing system, using DSP Starter Kit(DSK) of which the basic Processor is TMS302C6711 chip. The key ideas of this performance monitor is, using Real Time Data Exchange(RTDX) for the Purpose of real-time data transfer and function of DSP/BIOS, the ability to measure the Performance measure like DSP workload, memory usage, and bridge traffic. In the simulation, FFT, 2D FFT, Matrix Multiplication, and Fir Filter, which are widely used DSP algorithms, have been employed. Using performance monitor and Code Composer Studio from Texas Instrument(Tl) , the result has been recorded according to different frequencies, data sizes, and buffer sizes for a single wave file. The accuracy of our performance monitor has been verified by comparing those recorded results.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.39B no.7
• /
• pp.425-432
• /
• 2014

This paper proposes a wear-leveling algorithm that exploits the properties of SSD memories with multi-channel and multi-way architecture. When a write request arrives, the proposed algorithm classifies the stored data in DRAM buffer into hot or cold according to logical address access frequency, and performs data allocation to reduce deviation of block erase counts. It lowers the chance of increasing erase count by allocating cold data to blocks which have high erase count. Effectiveness of the proposed algorithm is verified by executing various applications on a multi-channel, multi-way SSD simulator. Experimental results show that differences in erase count among blocks is reduced by an average of 9.3%, and total erase count decreases by 4.6%, when compared to previous wear-leveling algorithm.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.12
• /
• pp.149-155
• /
• 2012

SSD is a storage device of having high-performance controller and cache buffer and consists of many NAND flash memories. Because NAND flash memory does not support in-place update, valid pages are invalidated when update and erase operations are issued in file system and then invalid pages are completely deleted via garbage collection. However, garbage collection performs many erase operations of long latency and then it reduces I/O performance and increases wear leveling in SSD. In this paper, we propose a new method of de-duplicating valid data and recycling invalid data. The method de-duplicates valid data and then recycles invalid data so that it improves de-duplication ratio. Due to reducing number of writes and garbage collection, the method could increase I/O performance and decrease wear leveling in SSD. Experimental result shows that it can reduce maximum 20% number of garbage collections and 9% I/O latency than those of general case.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.20 no.10
• /
• pp.126-134
• /
• 2006

This paper describes the development of an embedded wireless LAN controller which can be in parallel operated with an existing utility controller. The embedded controller mainly consists of Prism(R) 2.5 chip set and Atmega 128 microcontroller. In order to communicate over the network, the controller including TCP/IP stack (IP, TCP, UDP, and ICMP), telnet, and X/Z modem has been developed. For a specific application, we have proposed an special method to convert data structure between TCP/IP and X/Z modem and a data buffer algorithm to minimize the RAM memory usage. Finally, the correctness and performance of the protocols are tested and verified using $CommView^{(R)}\;and\;DU^{(R)}$. The development is satisfactorily operated only for 3,381 bytes of RAM usage without sacrificing interoperability between hosts.

• Proceedings of the KIEE Conference
• /
• 2002.07d
• /
• pp.2344-2346
• /
• 2002

A vacuum control system has been developed for using Ethernet Multi Serial Device Severs (EMSDS) for the Pohang Accelerator Laboratory (PAL) storage ring. There are 124 vacuum ion pumps at the storage ring. It was a very important problem to solve the problem how to control such a big number of vacuum pumps distributed around the ring. After discussions, we decided to develop a serial to ethernet interrace device sever that will be mounted in the control system rack. It has a 32-bits microprocessor embedded Linux, 12 ports RS485 (or RS232) slave interface. one channel 10/100BaseTx ethernet host port, one channel UART host port, and 16 Mbytes large memory buffer. These vacuum pumps are connected to Ion-Pump serial controllers, which chop the AC current so as to control the current in the pumps. The EMSDS connect either 100BaseTx or 10BaseT ethernet networks to asynchronous serial ports for communication with serial device. It can simultaneously control up to 12 ion-pump serial controllers. 12 EMSDS are connected to a personal computer (PC) through the network. The PC can automatically control the EMSDS by sending a set of commands through the TCP/IP network. Upon receiving a command from a PC running under Windows2000 through the network, the EMSDS communicate through the stave serial interrace ports to ion-pump controller. We added some software components on the top of EPICS (Experimental Physics and Industrial Control System) toolkit.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.15 no.6
• /
• pp.181-186
• /
• 2015

With the rapid growth of semiconductor technologies, small-sized devices with powerful computing abilities are becoming a reality. As this environment has a limit on power supply, NVM storage that has a high density and low power consumption is preferred to HDD or SSD. However, legacy software layers optimized for HDDs should be revisited. Specifically, as storage performance approaches DRAM performance, existing I/O mechanisms and software configurations should be reassessed. This paper explores the challenges and implications of using NVM storage with a broad range of experiments. We measure the performance of a system with NVM storage emulated by DRAM with proper timing parameters and compare it with that of HDD storage environments under various configurations. Our experimental results show that even with storage as fast as DRAM, the performance gain is not large for read operations as current I/O mechanisms do a good job hiding the slow performance of HDD. To assess the potential benefit of fast storage media, we change various I/O configurations and perform experiments to quantify the effects of existing I/O mechanisms such as buffer caching, read-ahead, synchronous I/O, direct I/O, block I/O, and byte-addressable I/O on systems with NVM storage.

• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.35T no.3
• /
• pp.46-52
• /
• 1998

In this paper, after inputting the computer with the attached number plate on the vehicle, using it, the color decomposition method and back propagation neural network proposed the extractable method of the vehicle number plate at high speed. This method separated R, G, B signal form input moving vehicle image to computer through video camera, then after transform this R, G, B signal into input image data of the computer by using color depth of vehicle number plate and store up binary value in the memory frame buffer. After adapting character's recognition algorithm, also improving this, by adapting back propagation neural network makes the vehicle number plate recognition system. Also minimalizing the similar color's confusion, adapting horizontal and vertical extracting algorithm by using the vehicle's rectangular architecture shows the extract and character's recognition of the vehicle number plate at high speed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.788-791
• /
• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.313-315
• /
• 2010

In this paper, we describe research results of developing hardware rasterizer that is applicable to mobile 3D graphics system, designed in SIMD architecture and verified in FPGA. Tile-based scan conversion unit is designed like SIMD architecture running four tiles simultaneously and each tile traverses pixels hierarchical in 3-level so that visiting counts is minimized. As experimental results, $8{\times}8$ is the most efficient size of tile and the last step of tile traversing is performed on $2{\times}2$ sized subtile. The rasterizer supports flat shading and gouraud shading and texture mapper supports affine mapping and perspective corrected mapping. Also, texture mapper supports point sampling mode and bilinear interpolating sampling mode and two types of wrapping modes and various blending modes. The rasterzer operates as 120Mhz on xilinx vertex4 $l{\times}100$ device. To easy verification, texture memory and frame buffer are generated as block rom and block ram.