• The Korean Journal of Financial Management
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• v.27 no.1
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• pp.63-87
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• 2010

This paper empirically examines whether ownership disperses when a venture firm its IPO (initial public offerings). The data for this study were collected from 91 firms that were initially listed on KOSDAQ between January 1, 2004 and December 31, 2007. We explored the influence of the underpricing of IPO on the change of large shareholders. The first finding of this investigation is that the number of shareholders of the venture firms who underpriced IPOs still increased after the closing of lockup. This is consistent with the findings of Booth and Chua(1996) and Brennan and Franks(1997). Second, the share of the large stockholders of the venture firms that a venture capital company invested decreased significantly after the end of lockup. Third, the venture businesses with higher ratio of flotation showed a significant decreasing of shareholders after the closing of lockup.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.141-144
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• 2000

In this paper, a new parallel array structure for the asynchronous array multiplier is introduced. This structure is designed for a data dependent asynchronous multiplier to reduces power which is wasted in conventional array structure. Simulation shows that this structure saves 30％ of power and 55％ of computation time comparing to conventional booth encoded array multiplier.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.145-148
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• 2000

A 16bit asynchronous multiplier has been designed using micropipelind structure with 2 phase and data bundling. And 4-radix modified Booth algorithm, CPlatch(Cature-Pass latch) and modified 4-2 counters have adopted in this design. It is implemented in 0.65$\mu\textrm{m}$ double-poly/double-metal CMOS technology by using 12,074 transistors with core size of 1.4${\times}$1.8$\textrm{mm}^2$. And our design results in a computation rate 55MHz a supply voltage of 3.3V.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.801-804
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• 2005

In this paper, we designed an 8-bit color adjustor for SDTV using Verilog HDL. The conversion block requires a lot of multiplication. So we adopted Booth algorithm to reduce amount of operation and processing time. To improve speed, we designed the system output as parallel structure. We synthesized the designed system using Xilinx ISE and verified the operation through simulation using Modelsim.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1085-1088
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• 1998

In this paper, we propose a hardware reduced multiplier for DSP applications. In many DSP application, all of multiplier products were not used, but only upper bits of rpoduct were used. Kidambi proposed truncated unsigned multiplier for this idea. In this paper, we abopt this scheme to Booth multiplier which can be used for real DSP systems. Also, zero input guarantees zero output that was not provided in the previous work.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1025-1028
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• 1998

Hardware to implement the parallelized Floating-point rounding algorithm is described. For parallelized additions, we propose an addition module which has carry selection logic to generate two results accoring to the input valuse. A multiplication module for parallelized multiplications is also proposed to generate Sum and Carry bits as intermediate results. Since these modules process data in IEEE standard Floatingpoint double precision format, they are designed for 53-bit significands including hidden bits. Multiplication module is designed with a Booth multiplier and an array multiplier.

• 한국초전도학회:학술대회논문집
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• v.13
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• pp.11-11
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• 2003

• 한국초전도학회:학술대회논문집
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• v.13
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• pp.39-39
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• 2003

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.99-105
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• 1994

Most of the companies are forced to cut down the manufacturing cost to survive in the competitive environment. Among others, material distribution cost alone takes substantial portion of the total manufacturing cost. In this study, we investigate the waiting phenomenon in the toll gate and propose a new toll booth layout to reduce the waiting time, thereby reduce the total material distribution cost. SIMAN, a simulation language, is employed to evaluate the proposed layout. The experimental results show that the layout reduces the waiting time significantly. Furthermore, the result indicates that determination of the intermediate buffer space affects the performance of the proposed layout.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.4
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• pp.11-20
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• 1996

1994년 9월7일부터 15일까지 9일간 미국 Chicago에서 International Manufacturing Technogy Show(IMTS 94)가 개최되어 수십만명이 Show를 보기 위해서 세계 각국으로부터 모여들고 있었다. 필자도 그 중 한사람이었으며 Gidding & Lewis사의 전시 Booth에 도착했을 때 어떤 기계의 Demo 를 구경하기 위한 인파가 꽉 차 있는 것을 보았다. 먼 곳에서 보니 1969.7.20 미국에서 달에 쏘아올려 Neil Armstrong이 조종한 Apollo ll 우주선과 흡사한 모습의 기계가 보였다. 상하 두 Platform 사이를 6개의 다리로 지지되어 있고 상부 Platform의 하축에 공구의 Spindle이 부착되어 있었다. 이 기계를 VARIAX라고 부르고 미래의 공작기계가 이모양이 될 것이라고 설명하고 있었다.