• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.306-313
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• 2007

In this paper, we efficiently implemented turbo code algorithm in FPGA H/W(hardware) resource. The used turbo code algorithm has the characteristics; the size of constraint is 3, encoder type is 1/3, the size of random interleaver is 2048. The proposed H/W consists of MAP block for calculating alpha and delta using delta value, storing buffer for each value, multiplier for calculating lamda, and lamda buffer. The proposed algorithm and H/W architecture was verified by C++ language and was designed by VHDL. Finally the designed H/W was programmed into FPGA and tested in wireless communication environment for field availability. The target FPGA of the implemented H/W is VERTEX4 XC4VFX12-12-SF363 and it is stably operated in 131.533MHz clock frequency (7.603ns).

• Journal of electromagnetic engineering and science
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• v.6 no.3
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• pp.147-154
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• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.6
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• pp.855-865
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• 1999

This paper presents the improvement of BER performance using fading compensation method for 16 QAM-TCM to reduce the effects of multi-path fading in mobile radio environments. We propose the multi-pilot symbol aided fading compensation technique using Gausian interpolation method for inter-symbol interference or fading distortion occured in frequency selective fading channel. The proposed system is combined coding and modulation scheme for improving the reliability of a digital transmission system without increasing the transmitted power or the required bandwidth. In the fading compensation, the pilot symbols from a known sequence is multiplexed into the data symbols at regular intervals to from a frames for transmission. And we use a modified bit reversal block interleaver to randomize burst errors. The results show that significant improvements in the bit-error rate performances can be achieved by the proposed techniques.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.1-11
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• 1997

We developed a base station modulator ASIC for CDMA digital cellular system. In CDMA digital cellular system, the modulation is performed by convolutional encoding and QPSK with spread spectrum. The function blocks of base station modulator are CRC, convolutional encoder, interleaver pseudo-moise scrambler, power control bit puncturing, walsh cover, QPSK, gain controller, combiner and multiplexer. Each function block was designed by the logic synthesis of VHDL codes. The VHDL code was described at register transfer level and the size of code is about 8,000 lines. The circuit simulation and logic simulation were performed by COMPASS tools. The chip (ES-C2212B CMB) contains 25,205 gates and 3 Kbit SRAM, and its chip size is 5.25 mm * 5,45 mm in 0.8 mm CMOS cell-based design technology. It is packaged in 68 pin PLCC and the power dissipation at 10MHz is 300 mW at 5V. The ASIC has been fully tested and successfully working on the CDMA base station system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.5
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• pp.1083-1096
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• 1997

To implement satellite B-ISDN/ATM network, it needs to gurantee reliable transport via satelite in the poor BER environment. So, it requires to use channel coding (FEC:Forward Error Correction) schemes for improvement of BER performance, but these coding effects evoke burst errors and degradation of the QoS. Therefore we have to investigate new algorithm that compensates these weaknesses. We consider convolutional coding and concatenated coding among FEC schemes as FEC for satellite transmission and choose different compensational algorithm by the error characteristics of the using type of FEC. In using concatenated coding, this paper proposes the satellite system structure for interconnection to the terrestrial network and proposes the channel coding algorithm for improvement of transmission performances. We execute performance evaluation of the proposed algorithm by computer simulation. In detail, we propose 4 types of application ATM cell to the block coding(Reed-Solomon) and propose the new 55 byte ATM cell that enforces the error correction capability of cell header by the BCH coding. Then we propose the outer interleaverand the cell unit interleaver that evoke maximum coding effect of BCH code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.3A
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• pp.173-179
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• 2002

In this paper, we suggest more precise performance analysis method of turbo interleavers based on two criteria; performance bounds like Union Bound and weight frequency of codewords. In order to present our new method, we employ block pseudo random, and so-called prime interleavers in compliance of 3GPP standard, respectively, We also applied this method to S-random interleavers that have different window size, S. 3GPP complied turbo encoder, decoder, and AWGN channel are implemented by using MATLAB for our performance analysis. According to our analysis, both criteria should be taken into account coincidently to predict the performance of newly designed interleavers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1563-1570
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• 1999

This paper relates to the soft decision method with erasure technique in digital terrestrial television broadcasting system. The proposed decoder use the CSI derived from using the pilots in receiver. The active real(I) and imaginary(Q) data are transferred to the branch metric calculation block that decides the Euclidean distance for the soft decision decoding and also the estimated CSI values are transferred to the same block. After calculating the Euclidean distance for the soft decision decoding, the Euclidean distance of branch metric is multiplied by CSI. To do so, new branch metric values that consider each carrier state information are obtained. We simulated this method in better performance of about 0.15dB to 0.17dB and 2.2dB to 2.9dB in Rayleigh channel than that of the conventional soft decision Viterbi decoding with or without bit interleaver where the constellation is QPSK, 16-QAM and 64-QAM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1006-1013
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• 2008

CZZ (Concatenated Zigzag) Code is a class of fast encodable LDPC codes. In the case that LDPC codes including CZZ codes have short length, short cycles seriously affect the code performance. In this paper, we construct CZZ codes using various degree-2 polynomial interleavers which eliminate cycles of length 4 and through simulation, compare the performance of these CZZ codes and turbo codes in many different fading channels. Especially, quasi-static fading channel, block fading channel, uncorrelated fading channel, and correlated fading channel are considered. Since CZZ codes show similar performance as turbo codes, they can be used in the next generation wireless communication systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.7A
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• pp.994-1004
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• 2000

In this paper, bitstreams are composed of using H.263 for a moving picture coding in the band-limited and error-prone environment such as wireless environment. EREC sub-frames are implemented by applying the proposed EREC algorithm in order to be UEP for the real data parts of implemented bitstreams. Because those are able to do resynchronization with a block unit, propagation of the error can be minimized, and the position of the important bits such as INTRADC and MVD can be known. Class is separated using the position of these important bits, and variable puncturing tables are designed by the class informations and the code rates of turbo codes are differently designed in according to the class. Channel coding used the turbo codes, and an interleaver to be designed in the turbo codes does not eliminate redundancy bits of the important bits in applying variable code rates of EREC sub-frames unit and is always the same at the transmitter and the receiver although being variable frame size. As a result of simulation, UEP with the code rate similar to EEP is obtained a improved result in the side of bit error probability. And the result of applying it to image knows that the subjective and objective quality have been improved by the protection of important bits.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.27-34
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• 2005

Iterative detection (ID) has proven to be a near-optimal solution for concatenated Finite State Machines (FSMs) with interleavers over an additive white Gaussian noise (AWGN) channel. When perfect channel state information (CSI) is not available at the receiver, an adaptive ID (AID) scheme is required to deal with the unknown, and possibly time-varying parameters. The basic building block for ID or AID is the soft-input soft-output (SISO) or adaptive SISO (A-SISO) module. In this paper, Reduced State SISO (RS-SISO) algorithms have been applied for complexity reduction of the A-SISO module. We show that serially concatenated CPM (SCCPM) with AID has turbo-like performance over fading ISI channels and also RS-A-SISO systems have large iteration gains. Various design options for RS-A-SISO algorithms are evaluated. Recently developed density evolution technique is used to analyze RS-A-SISO algorithms. We show that density evolution technique that is usually used for AWGN systems is also a good analysis tool for RS-A-SISO systems over frequency-selective fading channels.