• Title/Summary/Keyword: Block encryption

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Low Power Implementation of Integrated Cryptographic Engine for Smart Cards (스마트카드 적용을 위한 저전력 통합 암호화 엔진의 설계)

  • Kim, Yong-Hee;Jeong, Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.80-88
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    • 2008
  • In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.

A Pipelined Design of the Block Cipher Algorithm SEED (SEED 블록 암호 알고리즘의 파이프라인 하드웨어 설계)

  • 엄성용;이규원;박선화
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.3_4
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    • pp.149-159
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    • 2003
  • The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.

Speed-optimized Implementation of HIGHT Block Cipher Algorithm (HIGHT 블록 암호 알고리즘의 고속화 구현)

  • Baek, Eun-Tae;Lee, Mun-Kyu
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.22 no.3
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    • pp.495-504
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    • 2012
  • This paper presents various speed optimization techniques for software implementation of the HIGHT block cipher on CPUs and GPUs. We considered 32-bit and 64-bit operating systems for CPU implementations. After we applied the bit-slicing and byte-slicing techniques to HIGHT, the encryption speed recorded 1.48Gbps over the intel core i7 920 CPU with a 64-bit operating system, which is up to 2.4 times faster than the previous implementation. We also implemented HIGHT on an NVIDIA GPU equipped with CUDA, and applied various optimization techniques, such as storing most frequently used data like subkeys and the F lookup table in the shared memory; and using coalesced access when reading data from the global memory. To our knowledge, this is the first result that implements and optimizes HIGHT on a GPU. We verified that the byte-slicing technique guarantees a speed-up of more than 20%, resulting a speed which is 31 times faster than that on a CPU.

Implementation of Rijndael Block Cipher Algorithm

  • Lee, Yun-Kyung;Park, Young-Soo
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.164-167
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    • 2002
  • This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.

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Measuring Email User Reliability in a Blockchain Environment (블록체인 환경에서 Email 사용자 신뢰도 측정)

  • Kim, Daehan;Seo, Kyungryong
    • Journal of Korea Multimedia Society
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    • v.23 no.8
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    • pp.1030-1039
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    • 2020
  • The biggest feature of the online environment is anonymity. So it is difficult to identify the sender accurately in Email. So we use PGP to enhance the security of email. PGP is an e-mail encryption program that has become the standard for email security worldwide. But PGP has a weak point in security. PGP can identify users, but it is difficult to verify reliability. In PGP, the more reliable other users guarantee that user are, the more reliable they are. In the previous study, the PGP structure was implemented by utilizing the block chain to lay the foundation, and in this paper, the structure of the previous article is applied to the e-mail environment to measure up the sender's reliability, and a system is proposed that allows users to distinguish the reliability of the message.

Development of Media Crypto Algorithm for anti-hacking into CCTV (CCTV 해킹방지를 위한 미디어 암호화 알고리즘)

  • Hwang, Seon-Cheol
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.62 no.2
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    • pp.98-102
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    • 2013
  • There are so many CCTV in our streets, buildings and public places. Nevertheless, security methods for CCTV are rarely. This paper describes a study on developing a media crypto algorithm for anti-hacking into CCTV. H.264 codec is used to compress the video stream in CCTV systems. HIGHT algorithm provided by KISA is adopted as a crypto algorithm in our development. Other crypto methods except HIGHT could be selected by company's security police. Only some bytes in VCL(Video Coding Layer) of H.264 are encrypted to improve the performance of limited platforms, such as CCTV, WebCam, smartphone. Very fast and light crypto algorithm was developed by our researches.

Design of Efficient Partial Block Encryption Algorithm Based on File Type (파일 특성 기반 효율적인 부분 블록 암호화 알고리즘 설계)

  • Lee, Nam-Uk;Yang, Seung-Su;Park, Seok-Cheon
    • Proceedings of the Korea Information Processing Society Conference
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    • 2017.04a
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    • pp.382-383
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    • 2017
  • 최근 클라우드 기반의 스토리지 서비스가 지속적으로 성장하고 있다. 클라우드 스토리지 서비스는 데이터의 가용성 및 기밀성을 보장하기 위하여 다양한 암호화 방식을 사용한다. 그러나 기존 암호화 방식은 대용량 데이터 전송 시 처리 및 전송 속도가 저하되는 문제점이 발생한다. 이를 개선하기 위하여 파일 특성을 고려한 효율적인 부분 암호화 알고리즘을 설계하였다.

FPGA Implementation of Riindael Algorithm according to the Three S-box Implementation Methods (Rijndael S-box의 세 가지 구현 방법에 따른 FPGA 설계)

  • 이윤경;박영수;전성익
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.281-284
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    • 2002
  • Rijndael algorithm is known to a new private key block cipher which is substitute for DES. Rijndael algorithm is adequate to both hardware and software implementation, so hardware implementation of Rijndael algorithm is applied to high speed data encryption and decryption. This paper describes three implementation methods of Rijndael S-box, which is important factor in performance of Rijndael coprocessor. It shows synthesis results of each S-box implementation in Xilinx FPGA. Tllc lilree S-box implementation methods are implementation using lookup table only, implementation using both lookup table and combinational logic, and implementation using combinational logic only.

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An Optimum Architecture for Implementing SEED Cipher Algorithm with Efficiency (효율적인 SEED 암호알고리즘 구현을 위한 최적화 회로구조)

  • Shin Kwang-Cheul;Lee Haeng-Woo
    • Journal of Internet Computing and Services
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    • v.7 no.1
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    • pp.49-57
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    • 2006
  • This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 12B-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array, This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We have designed the circuit with the VHDL coding, implemented with a FPGA of 50,000 gates.

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Efficient Group Key Agreement Protocol (EGKAP) using Queue Structure (큐 구조를 이용한 효율적인 그룹 동의 방식)

  • Hong, Sung-Hyuck
    • Journal of Digital Convergence
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    • v.10 no.4
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    • pp.217-222
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    • 2012
  • Group communication on the Internet is exploding in popularity. Video conferencing, Enterprise IM, desktop sharing, and numerous forms of e-commerce are but a few examples of the ways in which the Internet is being used for business. The growing use of group communication has highlighted the need for advances in security. There are several approaches to securing user identities and other information transmitted over the Internet. One of the foundations of secure communication is key management, a building block for encryption, authentication, access control, and authorization.