• Journal of Computing Science and Engineering
• /
• 제3권1호
• /
• pp.15-26
• /
• 2009

Given an n-length text T over a $\sigma$-size alphabet, we present a compressed representation of T which supports retrieving queries of rank/select/access and updating queries of insert/delete. For a measure of compression, we use the empirical entropy H(T), which defines a lower bound nH(T) bits for any algorithm to compress T of n log $\sigma$ bits. Our representation takes this entropy bound of T, i.e., nH(T) $\leq$ n log $\sigma$ bits, and an additional bits less than the text size, i.e., o(n log $\sigma$) + O(n) bits. In compressed space of nH(T) + o(n log $\sigma$) + O(n) bits, our representation supports O(log n) time queries for a log n-size alphabet and its extension provides O(($1+\frac{{\log}\;{\sigma}}{{\log}\;{\log}\;n}$) log n) time queries for a $\sigma$-size alphabet.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제7권11호
• /
• pp.2941-2956
• /
• 2013

In this paper, we propose an effective fragile image watermarking scheme for tampering detection and content recovery. Cover image is divided into a series of non-overlapping blocks and a block mapping relationship is constructed by the secret key. Several DCT coefficients with direct current and lower frequencies of the MSBs for each block are used to generate the reference bits, and different coefficients are assigned with different bit numbers for representation according to their importance. To enhance recovery performance, authentication bits are generated by the MSBs and the reference bits, respectively. After LSB substitution hiding, the embedded watermark bits in each block consist of the information of itself and its mapping blocks. On the receiver side, all blocks with tampered MSBs can be detected and recovered using the valid extracted reference bits. Experimental results demonstrate the effectiveness of the proposed scheme.

• 전기학회논문지
• /
• 제56권2호
• /
• pp.428-431
• /
• 2007

A floating-point number system is used to represent a wide range of real numbers using finite number of bits. The standard the IEEE adopted in 1987 divides the range of real numbers into intervals of [$2^E,2^{E+1}$), where E is an Integer represented with finite bits, and defines equally spaced equal counts of discrete numbers in each interval. Since the numbers are defined discretely, not only the number representation itself includes errors but in floating-point arithmetic some strange behaviors are observed which cannot be agreed with the real world arithmetic. In this paper errors with floating-point number representation, those with arithmetic operations, and those due to order of arithmetic operations are analyzed theoretically with help of and verification with the results of some MATLAB program executions.

• 전자공학회논문지C
• /
• 제34C권3호
• /
• pp.23-36
• /
• 1997

In tis paper, sthe new data model for the hardware implementation of lempel-ziv compression algorithm was proposed. Traditional model generates the codeword which consists of 3 bytes, the last symbol, the position and the matched length. MSB (most significant bit) of the last symbol is the comparession flag and the remaining seven bits represent the character. We confined the value of the matched length to 128 instead of 256, which can be coded with seven bits only. In the proposed model, the codeword consists of 2 bytes, the merged symbol and the position. MSB of the merged symbol is the comression flag. The remaining seven bits represent the character or the matched length according to the value of the compression flag. The proposed model reduces the compression ratio by 5% compared with the traditional model. The proposed model can be adopted to the existing hardware architectures. The incremental factors of the compression ratio are also analyzed in this paper.

• 한국정보통신학회논문지
• /
• 제22권1호
• /
• pp.1-8
• /
• 2018

최근 합성곱 신경망은 컴퓨터 비전에 관련된 여러 분야에서 높은 성능을 보여 주고 있으나 합성곱 신경망이 요구하는 많은 연산양은 임베디드 환경에 도입되는 것을 어렵게 하고 있다. 이를 해결하기 위해 ASIC이나 FPGA를 통한 합성곱 신경망의 구현에 많은 관심이 모이고 있고, 이러한 구현을 위해서는 효율적인 고정 소수점 표현이 필요하다. 고정 소수점 표현은 ASIC이나 FPGA에서의 구현에 적합하나 합성곱 신경망의 성능이 저하될 수 있는 문제가 있다. 이 논문에서는 합성곱 계층과 배치(batch) 정규화 계층에 대해 고정 소수점 표현을 분리해서, ResNet-50 합성곱 신경망의 합성곱 계층을 표현하기 위해 필요한 비트 수를 16비트에서 10비트로 줄일 수 있게 하였다. 연산이 집중되는 합성곱 계층이 더 간단하게 표현되므로 합성곱 신경망 구현이 전체적으로 더 효율적으로 될 것이다.

• 정보통신설비학회논문지
• /
• 제10권2호
• /
• pp.80-85
• /
• 2011

In this paper, I propose flexible base point used for a BTC(Block Truncation Coding). Halftoning images are used for printer by reducing the number of pixel depth. During over 20 years, many researches have been studied to apply this techniques to image compression. BTC algorithms are the compression methods using digital halftoning technique about images. In the BTC algorithm, an image block is divided into higher and lower domain compared with the mean of block. then the MAX and MIN representative values are evaluated by calculating the mean of higher and lower domain respectively. At a result, an image block(for example 88 size) is compressed into 64bits pixel representation and 16 bits of the MAX and MIN. And they also have been tried to sustain the image quality high after compression. In this paper, I found that there is some marginal possibility to enhance the image quality by adjusting the base point(generally mean of block) of existing algorithms.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제12권7호
• /
• pp.3455-3474
• /
• 2018

As a unique form of signed-digit representation, non-adjacent form (NAF) minimizes Hamming weight by removing a stream of non-zero bits from the binary representation of positive integer. Thanks to this strong point, NAF has been used in various applications such as cryptography, packet filtering and so on. In this paper, to improve the NAF conversion speed of the $NAF_w$ algorithm, we propose a new NAF conversion algorithm, called w-bit Shifting Non-Adjacent Form($SNAF_w$), where w is width of scanning window. By skipping some unnecessary bit comparisons, the proposed algorithm improves the NAF conversion speed of the $NAF_w$ algorithm. To verify the excellence of the $SNAF_w$ algorithm, the $NAF_w$ algorithm and the $SNAF_w$ algorithm are implemented in the 8-bit microprocessor ATmega128. By measuring CPU cycle counter for the NAF conversion under various input patterns, we show that the $SNAF_2$ algorithm not only increases the NAF conversion speed by 24% on average but also reduces deviation in the NAF conversion time for each input pattern by 36%, compared to the $NAF_2$ algorithm. In addition, we show that $SNAF_w$ algorithm is always faster than $NAF_w$ algorithm, regardless of the size of w.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제10권11호
• /
• pp.5605-5623
• /
• 2016

We propose a face recognition method that utilizes the LCP face descriptor. The proposed method applies a LoG mask to extract a face contour response, and employs the LCP algorithm to produce a binary pattern representation that ensures high recognition performance even under the changes in illumination, noise, and aging. The proposed LCP algorithm produces excellent noise reduction and efficiency in removing unnecessary information from the face by extracting a face contour response using the LoG mask, whose behavior is similar to the human eye. Majority of reported algorithms search for face contour response information. On the other hand, our proposed LCP algorithm produces results expressing major facial information by applying the threshold to the search area with only 8 bits. However, the LCP algorithm produces results that express major facial information with only 8-bits by applying a threshold value to the search area. Therefore, compared to previous approaches, the LCP algorithm maintains a consistent accuracy under varying circumstances, and produces a high face recognition rate with a relatively small feature vector. The test results indicate that the LCP algorithm produces a higher facial recognition rate than the rate of human visual's recognition capability, and outperforms the existing methods.

• 방송공학회논문지
• /
• 제25권1호
• /
• pp.109-112
• /
• 2020

VVC는 화면 내 예측에서 67가지의 모드를 사용한다. 이때 화면 내 예측 모드 표현을 위한 데이터를 감소시키기 위하여 MPM(Most Probable Mode)을 사용한다. 시그널링 되는 모드가 MPM 후보 내에 존재하는 경우 MPM 리스트의 해당 index를 송신하는 방법을 사용하고 MPM 후보 내에 존재하지 않는 경우에는 TBC 부호화를 적용한다. 화면 내 예측에서 TBC가 적용될 때 MPM 후보를 제외하고 낮은 번호의 모드 순서대로 3가지가 선택되어 5비트로 부호화되고 나머지 모드는 6비트로 부호화된다. 본 논문에서는 VVC의 화면 내 예측에서 사용하는 TBC 기술의 한계점을 알아보고 화면 내 예측에서 TBC를 사용할 때 기존의 방법보다 효율적으로 부호화 할 수 있는 적응적인 방법을 제안한다. 그 결과 기존의 부호화 방법과 비교해서 overall 부호화 성능이 AI와 RA에서 각각 0.01%, 0.04%의 부호화 효율이 증대되었다.

• 정보과학회 논문지
• /
• 제44권5호
• /
• pp.537-544
• /
• 2017

부호가 있는 정수 표현의 특별한 형태인 NAF(non-adjacent form)는 양의 정수의 이진표현에서 0이 아닌 비트의 평균 밀도를 낮추어 해밍 웨이트를 최소화시킨다. 이러한 장점으로 인해 NAF는 다양한 분야에서 활용 가능하며 특히 암호학 분야에서 적극적으로 활용된다. 그러나 기존 NAF 변환 알고리즘은 변환 과정에서 LSB가 1이 되는 경우가 증가할수록 변환 속도가 저하되는 문제점이 존재한다. 본 논문에서는 기존 NAF 변환 알고리즘의 문제점을 해결하여 NAF 변환의 속도를 향상시키기 위한 방안을 제안한다. 제안한 알고리즘의 우수성을 검증하기 위하여 저성능 8-bit 마이크로프로세서인 ATmega128에 기존 알고리즘과 제안한 알고리즘을 구현하여 다양한 입력 패턴 하에서 CPU Cycle을 측정하였다. 이를 통해 제안 알고리즘이 기존 알고리즘보다 주요 패턴 처리 시 소요 사이클 카운터를 평균 20% 향상시킬 뿐만 아니라 NAF 변환 시간을 13% 이상 감소시킴을 확인하였다.