• 전자공학회논문지A
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• 제30A권9호
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• pp.59-70
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• 1993

An efficient test method based on march test is presented to cover line leakage failures associated with bit and word lines or mega bit DRAM chips. A modified column march (Y-march) pattern is derived to improve fault coverage against the data retention failure. Time delay concept is introduced to develop a new column march test algorithm detecting various data retention failures. A built-in test circuit based on the column march pattern is designed and verified using logic simulation, confirming correct test operations.

• 한국전자거래학회지
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• 제11권2호
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• pp.1-11
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• 2006

본 논문에서는 멀티 쉬프팅 기법을 이용한 효율적인 유한체의 역수 연산 알고리즘을 제안하고 있다. 연산 알고리즘의 효율성은 사용하는 기저에 따라 영향이 있음이 많은 선행 연구를 통해 알려져 왔으며, 보편적으로 다항식 기저와 최적 다항식 기저를 사용하여 연구하였다. 본 연구에서는 몽고메리 알고리즘에 바탕을 둔 멀티비트 쉬프팅 기법을 수정하고 구현하였다. 역수 연산을 수행하기 위해 본 연구에서 사용한 기약 다항식타입은 AOP와 3항식 이며, 수행 결과 26%까지의 성능향상을 보였다. 본 논문에서 제안한 알고리즘은 구현이 쉽고, 다양한 분야에서 응용이 가능하다.

• 한국통신학회논문지
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• 제24권8A호
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• pp.1227-1237
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• 1999

본 논문에서는 공평한 비밀정보 교환을 위한 기본 프로토콜인 불확정전송 프로토콜을 제안한다. 이를 위해 Lein Harn등이 앞서 제안한 이산대수문제에 기반을 둔 검증가능 불확정전송방식에 대하여 고찰하고 기존의 방식에다 부가적인 기능을 가지는 새로운 불확정전송 프로토콜을 제안한다. 이들의 방식에서 고려하지 않았던 송신자 확인 및 송신자의 송신사실 사후 부인방지 등의 여러 기능이 부가된 대화형 불확정전송 프로토콜을 제안한다. 이를 위해 Bit Commitment 기법을 이용하는 방법과 RSA에 기반한 디지털서명기법을 이용하는 두 가지 방법을 제안한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.305-308
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• 2002

An 1.8V 6bit IGSPS ADC for high speed data acquisition is discussed in this paper. This ADC is based on a flash ADC architecture because the flash ADC is the only practical architecture at conversion rates of IGSPS and beyond. A straightforward 6bit full flash A/D converter consists of two resistive ladders with 63 laps, 63 comparators and digital blocks. One important source of errors in flash A/D converter is caused by the capacitive feedthrough of the high frequency input signal to the resistive reference-lauder. Consequently. the voltage at each tap of the ladder network can change its nominal DC value. This means large transistors have a large parasitic capacitance. Therefore, a dual resistive ladder with capacitor is employed to fix the DC value. Each resistive ladder generates 32 clean reference voltages which alternates with each other. And a two-stage amplifier is also used to reduce the effect of the capacitive feedthrough by minimizing the size of MOS connected to reference voltage. The proposed ADC is based on 0.18${\mu}{\textrm}{m}$ 1-poly 6-metal n-well CMOS technology, and it consumes 307㎽ at 1.8V power supply.

• 한국산업정보학회논문지
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• 제17권3호
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• pp.19-26
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• 2012

RFID 시스템에서 중계 공격에 저항하기 위해 리더와 태그 간의 시도와 응답에 소요된 1비트의 왕복 여행시간 측정을 이용한 거리 한정 프로토콜이 주로 사용된다. 이러한 프로토콜에서 1비트 시도와 응답에 대한 중계 공격의 성공확률을 줄일 수 있으면 효율적인 거리 한정 프로토콜을 만들 수 있다. 본 논문에서는 Hancke와 Khun이 제안한 1비트 시도와 응답 기반의 RFID 거리 한정 프로토콜을 2비트 시도와 응답 기반으로 수정한 효율적인 RFID 거리 한정 프로토콜을 제안한다. n번의 시도와 응답에 대한 중계 공격의 성공확률이 제안된 프로토콜에서는 (7/16)n으로 (3/4)n인 Hancke와 Khun의 프로토콜보다 훨씬 낮다.

• 한국컴퓨터정보학회논문지
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• 제22권5호
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• pp.1-9
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• 2017

Recently, flash memory has been in a great demand from embedded system sectors for storage devices. However, program/erase (P/E) cycles per block are limited on flash memory. For the limited number of P/E cycles, many wear leveling techniques are studied. They prolonged the life time of flash memory using information tables. As one of the techniques, block erase table (BET) method using a bit array table was studied for embedded devices. However, it has a disadvantage in that performance of wear leveling is sharply low, when the consumption of memory is reduced. To solve this problem, we propose a novel wear leveling technique using Sampling-based Block Erase Table (SBET). SBET relates one bit of the bit array table to each block by using exclusive OR operation with round robin function. Accordingly, SBET enhances accuracy of cold block information and can prevent to decrease the performance of wear leveling. In our experiment, SBET prolongs life time of flash memory by up to 88%, compared with previous techniques which use a bit array table.

• 한국중재학회지:중재연구
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• 제23권4호
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• pp.29-53
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• 2013

Chinese ISD has been changed a lot since the reformation policy in 1978 and it is expected that China will present a changed attitude toward its advantage as its industrialization continues to advance. This study generally examines the ISD in BIT and also considers not only the attitude of China with regard to ISD but also the changes on the Chinese side. Moreover, this study determines the areas on which the Chinese government focuses. In order to conduct this study, the author attempts to classify the attitudes on ISD into chronical change and treaty powers based on the analysis of BIT. In addition, the paper examines the main contents of ISD in BIT which previously involved an agreement such as arbitral institution, arbitral range, counter-measures of local country, standard for admitting the nationality of corporate investors, and recognition and enforcement of arbitral award. Based on analysis, this paper mentions matters that require attention and caution in the Korea-China FTA as regards investment negotiation, and also suggests instructions for investors who may face dispute with the Chinese government.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 추계학술대회
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• pp.886-889
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• 2014

본 논문에서는 통신 신호를 도청하는 도청자가 존재하는 환경인 와이어탭(wiretap) 채널을 가정하여 하나의 피드백 비트를 이용한 직교 시공간 블록 코드(orthogonal space-time block code, OSTBC)의 물리계층 보안 성능을 평가한다. 여기서, 공간적 상관관계를 갖는 MIMO(multiple-input multiple-output) 채널을 가정한다. 본 논문에서는 하나의 피드백 비트를 이용한 OSTBC(one-bit feedback based OSTBC, F-OSTBC) 기술을 제시하고, 각 노드에서의 공간 채널 상관계수를 다양하게 가정하여 F-OSTBC와 기존의 OSTBC, 그리고 송신 안테나 선택 기술에 대한 보안 아웃티지 성능을 비교한다.

• ETRI Journal
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• 제25권6호
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• pp.510-516
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• 2003

In this paper, we describe the development of a platform-based SoC of a 32-bit smart card. The smart card uses a 32-bit microprocessor for high performance and two cryptographic processors for high security. It supports both contact and contactless interfaces, which comply with ISO/IEC 7816 and 14496 Type B. It has a Java Card OS to support multiple applications. We modeled smart card readers with a foreign language interface for efficient verification of the smart card SoC. The SoC was implemented using 0.25 ${\mu}m$ technology. To reduce the power consumption of the smart card SoC, we applied power optimization techniques, including clock gating. Experimental results show that the power consumption of the RSA and ECC cryptographic processors can be reduced by 32% and 62%, respectively, without increasing the area.

• 전자공학회논문지B
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• 제29B권11호
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• pp.111-119
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• 1992

In this paper, we propose an edge detection scheme for noisy images based on the co-occurrence matrix. In the proposed scheme based on the step edge model, the gray level information is simply converted into a bit-map, i.e., the uniform and boundary regions of an image are transformed into a binary pattern by using the local mean. In this binary bit-map pattern, 0 and 1 densely distributed near the boundary region while they are randomly distributed in the uniform region. To detect the boundary region, the co-occurrence matrix on the bit-map is introduced. The effectiveness of the proposed scheme is shown via a quantitative performance comparison to the conventional edge detection methods and the simulation results for noisy images are also presented.