• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.833-840
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• 1987

A new Block Truncation Coding(BTC) technique reducing the bit-plane and using differential pulse code modulation (DPCM) is proposed and compared with the conventional BTC methods. A new technique decides whether the subblock can be approximated to be uniform or not. If the subblock can be approximated to be uniform(merge mode), we transmit only the gray-level informantion. It not (split mode), we transmity both the bit-plane and the gray-level information. DPCM method is proposed to the encoding of gray-level information when the subblock can be approximated to be uniform. Also modified quantization method is presented to the encoding of gray-level information when the subblock is not uniform. This technique shows the results of coding 256 level images at the average data rate of about 0.75 bits/pel.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.161-164
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• 2000

The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.310-318
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• 2016

Emerging technologies such as the Internet of Things (IoT) and the Advanced Driver Assistant System (ADAS) often have image transmission functions with tough constraints, like low power and/or low delay, which require that they adopt line-based, low memory compression methods instead of existing frame-based image compression standards. Bit rate control in the conventional frame-based compression systems requires a lot of hardware resources when the scope of handled data falls at the frame level. On the other hand, attempts to reduce the heavy hardware resource requirement by focusing on line-level processing yield uneven image quality through the frame. In this paper, we propose a bit rate control that maintains consistency in image quality through the frame and improves the legibility of text regions. To find the line characteristics, the proposed bit rate control tests each line for ease of compression and the existence of text. Experiments on the proposed bit rate control show peak signal-to-noise ratios (PSNRs) similar to those of conventional bit rate controls, but with the use of significantly fewer hardware resources.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1996.06a
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• pp.175-180
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• 1996

In this paper, a new image segmentation method based on merging of two low contrast neighbor regions iteratively is proposed. It is suitable for very low bit rate coding. The proposed method reduces efficiently contour information and preserves subjective and objective image quality. It consists of image segmentation using 4-level hierarchical structure based on mathematical morphology and 1-level region merging structure using the contrast difference of two adjacent neighbor regions. For each segmented region of the third level, two adjacent neighbor regions having low contrast difference value in fourth level based on contrast difference value is merged iteratively. It preserves image quality and shows the noticeable reduction of the contour information, so that it can improve the bottleneck problem of segmentation-based coding at very low bit rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2032-2041
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• 1998

In this work, we propose a novel bit allocation method that is to minimize overall distortions subject ot the bit rate constraint. We partition the original bitallocation problem into 'macroblock level bit allocation' problems that can be solved by conventional Lagrangian mutiplier methods and a 'frame level bit allocation' problem. To tackle the frame level problem, 'two-phase optimization' algorithm is used with iter-frame dependency model. While the existing approaches are almost impossible to find the macroblock-unit result for the moving picture coding system due to high computational complexity, the proposed algorithm can drastically reduce the computational loads by the problem partitioning and can obtain the result close to the optimal solution. Because the optimally allocated results can be used as a benchmark for bit allocation methods, the upper performance limit, or a basis for approximation method development, we expect that the proposed algorithm can be very useful for the bit allocation related works.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.4
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• pp.679-684
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• 1994

Progressive transmission using optimum bit-ordering of discrete cosine transform(DCT) coded image is proposed to reconstruct a better image in a few bits among all the coded bits at the receiver. It is to transmit the bit gradually to reduce the distrotion of the reconstructed image most by transmitting one more bit. To do this, the power transfer factor(PTF) which is the squared value of difference between the reconstruction level of embedded quantizer and another reconstruction level made by transmitting one more bit is defined. And then, the transmission order of bits is obtained by sorting the PTFs of the coded bits. As a results, the proposed method can reconstruct image having less distortion and better quality at the same bit rate than the conventional zig-zag scan.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.5
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• pp.1728-1743
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• 2021

Three-dimensional (3D) video scenes are complex and difficult to control, especially when scene switching occurs. In this paper, we propose two algorithms based on an incremental proportional-integral-derivative (PID) algorithm and a similarity analysis between views to improve the method of bit allocation for multi-view high efficiency video coding (MV-HEVC). Firstly, an incremental PID algorithm is introduced to control the buffer "liquid level" to reduce the negative impact on the target bit allocation of the view layer and frame layer owing to the fluctuation of the buffer "liquid level". Then, using the image similarity between views is used to establish, a bit allocation calculation model for the multi-view video main viewpoint and non-main viewpoint is established. Then, a bit allocation calculation method based on hierarchical B frames is proposed. Experimental simulation results verify that the algorithm ensures a smooth transition of image quality while increasing the coding efficiency, and the PSNR increases by 0.03 to 0.82dB while not significantly increasing the calculation complexity.

• The Journal of the Korea Contents Association
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• v.11 no.8
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• pp.459-467
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• 2011

BIS(Bus Information Systems) supplies the bus arrived time information for users in using BIT(Bus Information Terminal) installed on the bus stop. BIT is the device using peoples directly. So, BIT need a quick response when it flew. These are an important factor in the strategy of the BIS maintenance. BIT need a maintenance cost to operate smoothly. So, Suppose that commercial advertisement can be displayed on BIT screen in this study. And we researched an advertisement rates of the optimum level in using Contingent Valuation Method. In addition, we analyzed a characteristic of user's depending on each time using multinomial Logit Modeling method, and studied for BIT operation and ad. displaying strategy considered user's sex, ages and using times.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7A
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• pp.775-780
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• 2004

In this paper, we propose a simple protection scheme for error prone bit positions of turbo codes using the error detection capability of the CRC, which is almost always employed in practical systems. The proposed scheme based on bit flipping with CRC offers flexibility on selecting the level of protection. Also, not having send additional parity bits or discarding useful bit positions, it offers the best error performance for a given level of protection.