• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1505-1512
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• 2009

This paper propose a new frame level rate control algorithm for improving video quality and decreasing quality variation of an entire video sequence in a very low bit rate environment. In the proposed scheme, the allocated bits to a GOP are distributed to each frame properly according to the frame characteristics as well as the buffer status and the channel bandwidth. The H.264 standard uses various coding modes and optimization methods to improve the compression performance, which makes it difficult to control the generated traffic accurately. In this paper, proper prediction models for low bit rate environments are lust proposed, and a target distortion is determined using the models. According to the target distortion, the bit budget is allocated to each frame. It is shown by experimental results that the new algorithm can generate the PSNR performance better than that of the existing rate control algorithm.

• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.429-440
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• 2007

A coded excitation has been studied to improve the performance for ultrasound imaging in term of SNR, imaging frame rate, contrast to tissue ratio, and so forth. However, it requires a complicated arbitrary waveform transmitter for each active channel that is typically composed of a multi-bit Digital-to-Analog Converter (DAC) and a linear power amplifier (LPA). Not only does the LPA increase the cost and size of a transmitter block, but it consumes much power, increasing the system complexity further and causing a heating-up problem. This paper proposes an optimized 1.5bit fourth order sigma-delta modulation technique applicable to design an efficient arbitrary waveform generator with greatly reduced power dissipation and hardware. The proposed SDM can provide a required SQNR with a low over-sampling ratio of 4. To this end, the loop coefficients are optimized to minimize the quantization noise power in signal band while maintaining system stability. In addition, the decision level for the 1.5 bit quantizer is optimized for a given input waveform, which results in the SQNR improvement of more than 5dB. Computer simulation results show that the SQNR of a FM(frequency modulated) signal generated by using the proposed method is about 26dB, and the peak side-lobe level (PSL) of its compressed waveform on receive is -48dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4C
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• pp.362-369
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• 2007

APSK (Amplitude Phase Shift Keying) digital modulation is characterized by the circular positioning of the transmission symbols in the constellation diagram. Due to such structural characteristics, the peak-to-average power ratio of the APSK modulation is lower than that of the QAM (Quadrature Amplitude Modulation), and the amount of performance degradation over nonlinear channels can be mitigated. The APSK modulation scheme has recently been adopted as satellite communication system standards including the DVB-S2 (Digital Video Broadcasting - Satellite, Version 2). In this paper, a BER (Bit Error Rate) upper bound approximation formula is derived using the channel model with the output power saturation characteristics, and its accuracy is demonstrated. Using the derived formula, the input power level that minimizes the BER is determined. The optimized performance based on the radii ratio of the 16APSK constellation and the channel saturation level is also presented.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.97-100
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• 2007

In order to overcome many defects in the current JPEG standard of still image compression, the new JPEG2000 standard has been development. The JPEG2000 standard is based on the principles of DWT and EBCOT Entropy Coding. EBCOT(Embedded block coding with optimized truncation) is the most important technology in the latest image-coding standard, JPEG2000. However, EBCOT occupies the highest computation time to operate bit-level processing. Therefore, many researches have achieved methods to minimize computation speed of EBCOT. Thus, this paper proposes the method of context-extraction that improves computational architecture. This paper proposes efficient context coding method. The proposed algorithm would apply to hard-wired JPEG2000 Encoder that is used for compression of high resolution image.

• Journal of Internet of Things and Convergence
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• v.9 no.4
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• pp.9-14
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• 2023

Recently, resource optimization research has been actively conducted in enterprises and data centers to manage the rapid growth of big data. In particular, thin provisioning, which allocates a large number of resources compared to fixedly allocated storage resources, has the effect of reducing initial costs, but as the number of resources actually used increases, the cost effectiveness decreases and the management cost for allocating resources increases. In this paper, we propose a technique that divides the physical blocks of flash memory into single-bit cells and multi-bit cells, formats them with a hybrid technique, and manages them by dividing frequently used hot data and infrequently used cold data. The proposed technique has the advantage that the physical and allocated resources are the same, such as thick provisioning, and can be used without additional cost increase, and the underutilized resources can be managed in multi-bit cell blocks, such as thin provisioning, which can allocate more resources than typical storage devices. Finally, we estimated the resource optimization effectiveness of the proposed technique through experiments based on simulations.

• Journal of IKEEE
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• v.16 no.3
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• pp.265-273
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• 2012

Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

• Journal of Internet Computing and Services
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• v.3 no.5
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• pp.9-17
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• 2002

CSIX-L1 is the Common Switch Interface that defines a physical interface for transferring information between a traffic manager (Network Processor) and a switching fabric in ATM, IP, MPLS, Ethernet and data communication areas. In Tx, data to be transmitted is generated in Cframe which is the base information unit and in Rx, original data is extracted from the received Cframe. CSIX-L1 suppots the 32, 64, 96, and 123-bit interface and generates a variable length CFrame and Idle Cframe. Also CSIX-L1 appends Padding byte and supports 16-bit Vertical parity, CSIX-L1 is designed using Xilinx 4,1i. After functional and timing simulations are completed. CSIX-L1 module is downloaded in Xilinx FPGA XCV1000EHQ240C and verified. The synthesized CSIX module operates at 27MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.2
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• pp.162-171
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• 1991

This paper presents an algorithm for compressing image data by separating the image into two parts. I.e. edge image containing high-frequency components and non-edge image containing low-frequency components of image. The edge image is extracted by using 8 level compass gradient masks and the non-edge image is obtained by removing the edge image from the original image. The edge image is coded by Huffman run-length code and the non edge image is transformed first by DCT and the transformed images is coded next by a quantized bit allocation table. For an example image. GIRL. the proposed algorithm shows bit rate of 0.52 bpp with PSNR of 36dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.54-60
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• 2006

In order to test the board with IEEE 1149.1 boundary scan design, the test sequence must be applied as the bit stream However it is very tedious job to generate the test bit sequence since it requires the complete hlowledge about the 1149.1. This fuper introduces a convenient PCI/USB interface controller, named as Test-Ready PCI (TRPCI) ard Test-Ready USB (TRUSB). Test Bus Controller has been developed by TI and Lucent aiming to generate the test bit stream as an instruction level, thus even the novice test engineer can easily generate the test sequence.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.129-132
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• 2002

AE64000 is the 64-bit high-performance microprocessor that ADC Co. Ltd. is developing for an embedded environment. It has a 5-stage pipeline and uses Havard architecture with a separated instruction and data caches. It also provides SIMD-like DSP and FP operation by enabling the 8/16/32/64-bit MAC operation on 64-bit registers. AE64000 processor implements the EISC ISA and uses the instruction folding mechanism (Instruction Folding Unit) that effectively deals with LERI instruction in EISC ISA. But this unit makes branch prediction behavior difficult. In this paper, we designs a branch predictor optimized for AE64000 Pipeline and develops a AES4000 simulator that has cycle-level precision to validate the performance of the designed branch predictor. We makes TAC(Target address cache) and BPT(branch prediction table) seperated for effective branch prediction and uses the BPT(removed indexed) that has no address tags.