• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.83-88
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• 2008

In this paper, a new scheduling method considering bit-level delays for high-level synthesis is proposed. Conventional bit-level delay calculation for high-level synthesis was usually limited for specific resources. However, we have developed an efficient bit-level delay calculation method which is applicable to various resources, in this research. This method is applied to scheduling. The scheduling algorithm is based on list scheduling and executes chaining considering bit-level delays. Furthermore, multi-cycle chaining can be allowed to improve performance under resource constraints. Experimental results on several well-known DSP examples show that our method improves the performance of the results by 14.7% on the average.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.12
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• pp.3037-3054
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• 2013

Interference between primary user (PU) and secondary user (SU) transceivers should be mitigated in order to implement underlay spectrum sharing in cognitive radio networks (CRN). Considering this scenario, an improved joint subcarrier and bit allocation scheme for cognitive user with primary users' cooperation (PU Coop) in CRN is proposed. In this scheme, the optimization problem is formulated to minimize the average interference power level at the PU receiver via PU Coop, which guarantees a higher primary signal to interference plus noise ratio (SINR) while maintaining the secondary user total rate constraint. The joint optimal scheme is separated into subcarrier allocation and bit assignment in each subcarrier via arith-metric geo-metric (AM-GM) inequality with asymptotical optimization solution. Moreover, the joint subcarrier and bit optimization scheme, which is evaluated by the available SU subcarriers and the allocated bits, is analyzed in the proposed PU Coop model. The performance of cognitive spectral efficiency and the average interference power level are investigated. Numerical analysis indicates that the SU's spectral efficiency increases significantly compared with the PU non-cooperation scenario. Moreover, the interference power level decreases dramatically for the proposed scheme compared with the traditional Hughes-Hartogs bit allocation scheme.

• ETRI Journal
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• v.24 no.4
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• pp.280-289
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• 2002

In this work, we present a novel approach to the bit allocation problem that aims to minimize overall distortion subject to a bit rate constraint. The optimal solution can be found by the Lagrangian method with dynamic programming. However, the optimal bit allocation for block-based interframe coding is practically unattainable because of the interframe dependency of macroblocks caused by motion compensation. To reduce the computational burden while maintaining a result close to the optimum, i.e., near optimum, we propose an alternative method. First, we present a partitioned form of the bit allocation problem: a "frame-level problem" and "one-frame macroblock-level problems." We show that the solution to this new form is also the solution to the conventional bit allocation problem. Further, we propose a bit allocation algorithm using a "two-phase optimization technique" with an interframe dependency model and a rate-distortion model.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.4
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• pp.25-32
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• 1997

In this paper, we propose an adaptive BTC algorithm using the characteristics of the error signals. The BTC algorithm has a avantage that it is low computational complexity, but a disadvantage that it produces the ragged edges in the reconstructed images for th esloping regions beause of coding the input with 2-level signals. Firstly, proposed methods classify the input into low, medium, and high activity blocks based on the variance of th einput. Using 1-level quantizer for low activity block, 2-level for medium, and 4-level for high, it is adaptive methods that reduce bit rates and the inherent quantization noises in the 2-level quantizer. Also, in case of processing high activity block, we propose a new quantization level allocation algorithm using the characteristics of the error signals between the original signals and the reconstructed signals used by 2-level quantizer, in oder that reduce bit rates superior to the conventional 4-level quantizer. Especially, considering the characteristics of input block, we reduce the bit rates without incurrng the visual noises.

• Journal of Korea Multimedia Society
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• v.9 no.2
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• pp.244-254
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• 2006

This paper presents an efficient hybrid technique to compact the trie indexing the huge forward table small enough to be stored into cache for speeding up IP lookup. It combines two techniques, an encoding scheme called bit-map and a controlled-prefix expanding scheme to replace slow memory search with few fast-memory accesses and computations. For compaction, the bit-map represents each index and child pointer with one bit respectively. For example, when one node denotes n bits, the bit-map gives a high compression rate by consumes $2^{n-1}$ bits for $2^n$ index and child link pointers branched out of the node. The controlled-prefix expanding scheme determines the number of address bits represented by all root node of each trie's level. At this time, controlled-prefix scheme use a dynamic programming technique to get a smallest trie memory size with given number of trie's level. This paper proposes standard that can choose suitable trie structure depending on memory size of system and the required IP lookup speed presenting optimal memory size and the lookup speed according to trie level number.

• Journal of Information Processing Systems
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• v.12 no.2
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• pp.322-331
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• 2016

Image compression is an essential technique for saving time and storage space for the gigantic amount of data generated by images. This paper introduces an adaptive source-mapping scheme that greatly improves bit-level lossless grayscale image compression. In the proposed mapping scheme, the frequency of occurrence of each symbol in the original image is computed. According to their corresponding frequencies, these symbols are sorted in descending order. Based on this order, each symbol is replaced by an 8-bit weighted fixed-length code. This replacement will generate an equivalent binary source with an increased length of successive identical symbols (0s or 1s). Different experiments using Lempel-Ziv lossless image compression algorithms have been conducted on the generated binary source. Results show that the newly proposed mapping scheme achieves some dramatic improvements in regards to compression ratios.

• Proceedings of the Korea Database Society Conference
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• 1995.12a
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• pp.173-176
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• 1995

본 논문에서 다루는 내용은 멀티미디어 정보처리시 이용되는 여러 신호 처리용 하드웨어에서 필요로 하는 벡터 트랜스퍼메이션(Vector Transformation)및 오소그날 트랜스퍼메이션(Orthogonal Transformation)에 유용할 뿐만 아니라 여러 형태의 다양한 연산(elementary function including trigonometric functions)을 하나의 단일화된 알고리즘으로 구현할 수 있게 한 CORDIC(Coordinate Rotation Digit Computer)연산［1］［2］에 관한 연구이다. CORDIC 연산기를 실현함에 있어서 고속 연산을 위해 고속 가산기(fast adder)로서 CSA(Carry Save Adder)를 선택하는데, 본 논문의 연구 초점은 CORDIC연산기를 하드웨어로 실현하기 전에 Bit-Level의 시뮬레이터를 통하여, CSA의 특징상 발생할 수 있는 문제점어 대해 설명하고, 해결 방법［3］을 이용하여 원하는 값에 접근하는가를 확인하여 다양한 Bit의 조작으로 오차의 정도에 따라 유효한 CORDIC연산기를 실현하는데 도움이 되고자 한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.26-27
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• 2006

To develop tera-bit level SONOS flash memories, SONOS unit memory and 64 bit flash arrays are fabricated. The unit cells have both channel length and width of 30nm. The NAND & NOR arrays are fabricated on SOI wafer and patterned by E-beam. The unit cells represent good write/erase characteristics and reliability characteristics. SSL-NOR array have normal write/erase operation. These researches are leading the realization of Tera-bit level non-volatile nano flash memory.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

• Journal of Korea Society of Industrial Information Systems
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• v.16 no.3
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• pp.23-33
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• 2011

In this paper, the wavelet image coder, that can encode the bit-level information of wavelet coefficients, is proposed. The proposed coder is used the modified EZW algorithm and significant coefficient array that has bit level information of the wavelet coefficients to reduce the memory requirement in coding process. The significant coefficient array is two dimensional data structure that has bit level information of the wavelet coefficients. The proposed algorithm performs the coding of the significance coefficients and coding of bit level information of wavelet coefficients at a time by using the significant coefficient array. Experimental results show a better or similar performance of the proposed method when compared with conventional embedded wavelet coding algorithm. Especially, the proposed algorithm performs stably without image distortion at various bit rates with minimum memory usage by using the significant coefficient array.