• Journal of the Korea Society for Simulation
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• v.14 no.1
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• pp.1-8
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• 2005

In the semiconductor manufacturing, yield enhancement is an urgent issue. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. Reviewing wafer level and composite lot level yield patterns has always been an effective way of identifying yield inhibitors and driving process improvement. This process is very time consuming and as such generally occurs only when the overall yield of a device has dropped significantly enough to warrant investigation. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map.

• Speech Sciences
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• v.3
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• pp.177-186
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• 1998

This paper describes the procedure of implementing a real-time speech codec, G.723.1 which was developed by DSP Group and standardized by ITU-T, using fixed-point DSP, ADSP-2181. This codec has two bit rates associated with it, 5.3 and 6.3 kbit/s. We implemented only one bit rate, 6.3 kbit/s, of the two with fixed-point 32-bit precision. According to the result of the experiment, the amount of computational burden is about 55 MIPS and its quality is similar to the result of the PC simulation with floating-point arithmetic. In this paper, we proposed a method to use a fixed-point DSP and a procedure for developing a real-time speech codec using DSPs and finally developed a G.723.l speech codec for ADSP-2181.

• Speech Sciences
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• v.10 no.4
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• pp.125-136
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• 2003

Speech coding techniques have been studied to reduce the complexity and bit rate but also to improve the sound quality. CELP type vocoder, has used as a one of standard, supports the great sound quality even low bit rate. In this paper, the preprocessing of input speech to reduce the bit rate is the different with the conventional vocoder. The different kinds of parameter are used for the preprocessing so this paper is compared with theses parameters for finding the more appropriate parameter for the vocoder. The parameters are used to synthesize the speech not to encode or decode for coding technique so we proposed the simple algorithm not to have the influence on the processing time or the computation time. The parameters in used the preprocessing step are speaking rate, duration and PSOLA technique.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.121-125
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• 2006

A new GPS receiver correlator for the deeply-coupled GPS/INS integration system is proposed in order to the computation time problem of the Kalman filter. The proposed correlator consists of two early, prompt and late arm pairs. One pair is for detecting data bit transition boundary and another is for the correlator value calculation between input and replica signal. By detecting the data bit transition boundary, the measurement calculation time can be made longer than data bit period. As a result of this, the computational time problem of the integrated Kalman filter can be resolved. The validity of the proposed method is given through computer simulations.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.8
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• pp.94-99
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• 2000

In this study applied the general controller into th 16bit ordinary controller and recommand the simulator features the real system's propeties without DSP(Digital Signal Processing)-card. This simulator is designed to be synchronized in real time using A/D(Analog-Digital) convert and D/A(Digital-Analong) convert. In this study DSP card which is usually used for complex calculation is replaced with personal computer and designed to control, control-force using with the 16-bit micro processor.

• Journal of IKEEE
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• v.24 no.2
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• pp.507-513
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• 2020

The median filter that is used in various fields requiring image processing converts to a median value of pixels belonging to a radius r for all pixels in the image of n×m size. For 8-bit depth images, an O(nm) time algorithm exists but for over 16-bit depth images, there is an O(nmlog²r) time algorithm of Gil and Werman. In this paper, we propose an efficient median filter algorithm that works for more than 16-bit depth images. The time complexity of our algorithm is the same as that of Gil and Werman, but theoretical analysis and experimental results show that ours is efficient than above two times.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.945-950
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• 2002

In this paper the performance evaluations on Asynchronous Transfer Mode(ATM) access node are performed in the ATM access network which consists of access node and channel. The performance factors of access node are Cell Loss Ratio(CLR), buffer capacity and delay time. Both the ATM cell-scale queueing model and burst-scale queueing model are considered as the traffic model of access node for various traffic types such as Constant Bit Rate(CBR), Variable Bit Rate(VBR) and random traffic in the ATM access networks. Based on these situations, the relation of CLR, buffer capacity and delay time is analyzed in the ATM access node.

• Journal of IKEEE
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• v.20 no.2
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• pp.167-170
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• 2016

Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.

• Geomechanics and Engineering
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• v.8 no.4
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• pp.477-493
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• 2015

In rock drilling, the most important characteristic to clarify is the wear of the drill bits. The reason that the rock drill bits fail with time is wear. In dry sliding contact adhesive wear deteriorates the materials in contact, quickly, and is the result of shear fracture in the momentary contact joins between the surfaces. This paper aims at presenting an overview of the assessment of WC/Co cemented carbide (CC) tricone bit in rotary drilling. To study wear of these bits, two approaches have been used in this research. Firstly, the new bits were weighted before they mounted on the drill rigs and also after completion their useful life to obtain bit weight loss percentage. The characteristics of the rock types drilled by using such this bit were measured, simultaneously. Alternatively, to measure contact wear, namely, matrix wear a micrometer has been used with a resolution of 0.02 mm at different direction on the tricone bits. Equivalent quartz content (EQC), net quartz content (QC), muscovite content (Mu), coarseness index (CI) of drill cuttings and compressive strength of rocks (UCS) were obtained along with thin sections to investigate mineralogical properties in detail. The correlation between effective parameters and bit wear were obtained as result of this study. It was observed that UCS shows no significant correlation with bit wear. By increasing CI and cutting size of rocks wear of bit increases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.