• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• Journal of the Korea Computer Industry Society
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• v.7 no.5
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• pp.513-520
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• 2006

In this paper, we propose a novel real-time frame-layer rate control algorithm using sliding window method for low bit rate video coding. The proposed rate control method performs bit allocation at the frame level to minimize the average distortion over an entire sequence as well as variations in distortion between frames. A new frame-layer rate-distortion model is derived, and a non-iterative optimization method is used for low computational complexity. In order to reduce the quality fluctuation, we use a sliding window scheme which does not require the pre-analysis process. Therefore, the proposed algorithm does not produce time delay from encoding, and is suitable for real-time low-complexity video encoder. Experimental results indicate that the proposed control method provides better visual and PSNR performance than the existing TMN8 rate control method.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.34-40
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• 1992

This paper shows a new relational formula of multiplexing gain versus variable input bit rates useful for designing Nx1 ATM(Asynchronous Transfer Mode) multiplexer which mixes several asynchronous bit streams with different transmission rates. The relation between multiplexing gain and input bit stream speeds is derived from the occupied mean lenght(the width per unit time) of cells and the occupation probability of the number of cells at an arbitrary instant when the rates of the periodic cell strams change randomly. And the relation between multiplexing gain and variable bit rates from different number of input bit streams is analyzed accordingly. Under the condition of unlimited multiplexing speed, the more number of input bit streams increases, the bigger the multiplexing gain becomes. While for the case which restricts the multiplexing speed to a limited value, the multiplexing gain becomes smaller contrarily as the number of input bit streams continues too invrease beyond a boundary value. It is shown that for designing an ATM multiplexer according to the latter case, the combination of input bit streams should be determined such as its total bit rate is lower thean, but most apprpaximate to, the multiplexed output speed. Also the general formula evaluating the most significant parameters which should be needed to design the multiplexer is derived.

• Journal of Broadcast Engineering
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• v.22 no.1
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• pp.42-50
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• 2017

A Bit-depth expansion is a method to increase the number of bit. It is getting important as the needs of HDR (High Dynamic Range) display or resolution of display have been increased because the level of luminance or expressiveness of color is proportional to the number of bit in the display. In this paper, we present effective bit-depth expansion algorithm for conventional standard 8 bit-depth content to display in high bit-depth device (10 bits). Proposed method shows better result comparing with recently developed methods in quantitative (PSNR) with low complexity. The proposed method shows 1db higher in PSNR measurement with 40 times faster in computational time.

• Fire Science and Engineering
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• v.17 no.3
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• pp.1-6
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• 2003

In this study, it reviewed about evacuation performance of a specified Office Building. assessment tools is FAST 3.1.7 (Estimation of Flash Over, Estimation of Layer Height Down Flow Time), SIMULEX 32-bit (Estimation of Evacuation Time), JASMINE 3.25d. (Smoke Flow Assessment of a specified time) Result from Fire Scenario # 1, Flash Over is not generated in Compartment. Evacuation Time is estimated 25.2 sec by SIMULEX 32-bit. layer height until this time (25.2 sec) was estimated 2.4 m by FAST 3.1.7. After ignition until this time (25.2 sec), smoke was not release to the a corridor. In consequence, We concluded that people in building are completing the safe evacuation without the damage of smoke. Result from Fire Scenario # 1, Flash Over generated 6 min 33.2 sec in Compartment. Evacuation Time is estimated 1 min 25.5 sec by SIMULEX 32-bit. layer height down flow time is 1 min 40.8 sec by FAST 3.1.7 and 5 min 23 sec by theoretical calculation. Also, total building evacuation time was estimated 2 min 26.6 sec. After ignition until this time (2 min 26.6 sec), smoke released to the a corridor but it amount was few little. Therefore, generated smoke in compartment not effected to the people in buildings.

• Journal of Convergence for Information Technology
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• v.11 no.9
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• pp.124-129
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• 2021

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.4
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• pp.63-71
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• 1996

In this paper, a variable length block code for real time compression and decompression of hanguel and chinese character bit map font is proposed. The proposed code shows a good compression ratio in complete form of hangeul myoungjo and godik style and chinese batang and doddum style bit map font. Besides, a compression and decompression ASIC is designed and simulated on CAD. The 0.8 micron CMOS sea of gate is used to implement the ASIC in amount of 5,200 gates, and it runs at simple hardware and compress and decompress at 33M bit/sec at maximum, which is ideal for real time applications.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2534-2536
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• 2002

This paper presents the design of high speed bit and word processor for sequence logic control using a FPGA. This FPGA is able to execute sequence instruction during program fetch cycle, because the program memory was separated from the data memory for high speed execution at 40MHz clock. Also this processor has 274 instructions set with a 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by V600EHQ240 and Foundation tool of Xilinx company. The final simulation was successfully performed under Foundation tool simulation environment. And the FPGA programmed by VHDL for a 240 pin HQFP package. Finally the benchmark was performed to prove that the designed for bit and word processor has better performance than Q4A of Mitsubishi for the sequence logic control.

• Journal of the Korea Society of Computer and Information
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• v.24 no.8
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• pp.137-142
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• 2019

This paper proposed bitmap based spatial data transmission scheme in need of rapid transmission through network in mobile environment that use and creation of data are frequently happen. Former researches that used clustering algorithms, focused on providing service using spatial data can cause delay since it doesn't consider the transmission speed. This paper guaranteed rapid service for user by convert spatial data to bit, leads to more transmission of bit of MTU, the maximum transmission unit. In the experiment, we compared arithmetically default data composed of 16 byte and spatial data converted to bitmap and for simulation, we created virtual data and compared its network transmission speed and conversion time. Virtual data created as standard normal distribution and skewed distribution to compare difference of reading time. The experiment showed that converted bitmap and network transmission are 2.5 and 8 times faster for each.