• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1074-1080
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• 2002

In clients/server environments, the one-time password scheme using time is especially useful because it solves the synchronization problem. However, it has the problem that is time-slippage, and causes the authentication to fail. In this paper, we propose an effective one-time password algorithm, which solves the time-slippage problem through the use of 1-bit information, which denotes the duration in which the authentication could be failed because of time-slippage. This algorithm is added easily and quickly to current one-time password systems using time without requiring any change of protocols: the proposed algorithm can be implemented by adding only 1-bit information to the user authentication information, not by modifying the one-time password authentication system protocol. And we propose also the algorithm of time correction, which can be implemented by adding 2-bit information on the proposed one-time password.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.857-865
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• 1995

In this paper, a nibble RLE(Run Length Encoding) code for real time compression and decompression of Hanguel bit map font and printer data is proposed. The nibble RLE code shows good compression ratio in complete form Hangeul Myoungjo and Godik style bit map font and printer output bit map data. And two ASICs seperating compression and decompression are designed and simulated on CAD to verify the proposed code. The 0.8 micron CMOS Sea of Gate is used to implement the ASICs in amount of 2, 400 gates, and these are running at 25MHz. Therefore, the proposed code could be implemented with simple hardware and performs 100M bit/sec compression and decomression at maximum, it is good for real time applications.

• ETRI Journal
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• v.41 no.2
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• pp.184-196
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• 2019

Wavelet packet modulation (WPM) is a multicarrier modulation (MCM) technique that has emerged as a potential alternative to the widely used orthogonal frequency-division multiplexing (OFDM) method. Because WPM has overlapped symbols, equalization cannot rely on the use of the cyclic prefix (CP), which is used in OFDM. This study applies linear minimum mean-square error (MMSE) equalization in the time domain instead of in the frequency domain to achieve low computational complexity. With a modest equalizer filter length, the imperfection of MMSE equalization results in subcarrier attenuation and noise amplification, which are considered in the development of a bit-loading algorithm. Analytical expressions for the bit error rate (BER) performance are derived and validated using simulation results. A performance evaluation is carried out in different test scenarios as per Recommendation ITU-R M.1225. Numerical results show that WPM with equalization-aware bit loading outperforms OFDM with bit loading. Because previous comparisons between WPM and OFDM did not include bit loading, the results obtained provide additional evidence of the benefits of WPM over OFDM.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.4
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• pp.1296-1309
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• 2023

In this paper, based on the soft cancellation (SCAN) bit-flipping (SCAN-BF) algorithm, a generalized SCAN bit-flipping (GSCAN-BF-Ω) decoding algorithm is carried out, where Ω represents the number of bits flipped or corrected at the same time. GSCAN-BF-Ω algorithm corrects the prior information of the code bits and flips the prior information of the unreliable information bits simultaneously to improve the block error rate (BLER) performance. Then, a joint threshold scheme for the GSCAN-BF-2 decoding algorithm is proposed to reduce the average decoding complexity by considering both the bit channel quality and the reliability of the coded bits. Simulation results show that the GSCAN-BF-Ω decoding algorithm reduces the average decoding latency while getting performance gains compared to the common multiple SCAN bit-flipping decoding algorithm. And the GSCAN-BF-2 decoding algorithm with the joint threshold reduces the average decoding latency further by approximately 50% with only a slight performance loss compared to the GSCAN-BF-2 decoding algorithm.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.149-152
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• 2002

The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.403-406
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• 1999

Among the compression methods of moving picture information, a motion estimation method is used to remove time-repeating. The Block Matching Algorithm in motion estimation methods is the commonest one. In recent days, it is required the more advanced high quality in many image processing fields, for example HDTV, etc. Therefore, we have to accomplish not by means of Partial Search Algorithm, but by means of Full Search Algorithm in Block Matching Algorithm. In this paper, it is suggested a structure that reduce total calculation quantity and size, because the structure using Bit Plane select and use only 3bit of 8bit luminance signal.

• ETRI Journal
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• v.26 no.6
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• pp.583-588
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• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.486-490
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• 2004

Programmable logic controller (PLC) is widely used in manufacturing system or process control. This paper presents the design of a 32-bit microprocessor for a sequence control using an Application Specification Integrated Circuit (ASIC). The 32-bit microprocessor was designed by a VHDL with top down method; the program memory was separated from the data memory for high speed execution of 274 specified sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. And in order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32-bits. And the real time debugging as single step run, break point run was implemented. Pulse instruction, step controller, master controllers, BIN and BCD type arithmetic instructions, barrel shit instructions were implemented for many used in PLC system. The designed microprocessor was synthesized by the S1L50000 series which contains 70,000 gates with 0.65um technology of SEIKO EPSON. Finally, the benchmark was performed to show that designed 32-bit microprocessor has better performance than Q4A PLC of Mitsubishi Corporation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.4
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• pp.64-69
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• 2009

Bit-interleaved coded modulation(BICM) applied to Alamouti's orthogonal space-time block code(OSIBC) has a rate loss problem In this paper, we expand orthogonal space-time block code(OSTBC) and apply bit-interleaved coded modulation (BICM) to expanded OSTBC(XOSIBC) to obtain a diversity gain without a rate loss. Binary phase shift keying(BPSK) design example is presented. Simulation results are also provided.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.3
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• pp.34-39
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• 2008

In this paper, we propose a bit-interleaved coded modulation (BICM) a lied to improved super-orthogonal space-time block code(SOSTBC). The proposed system achieves a greater diversity gain than that of super-orthogonal space-time trellis code (SOSTTC) with similar decoding complexity. Since, using the improved SOSTBC, the bit diversity carl be full diversity of SOSTBC. In contrast, BICM applied to Jafarkhani's SOSTBC is difficult to achieve a greater diversity gain than that of SOSTTC, because every bit diversity of the system is 1.