• Journal of KIISE
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• v.43 no.1
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• pp.34-39
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• 2016

JavaScript is widely used in web pages with HTML. Many JavaScript engines adopt Just-in-time compilers to accelerate the execution of JavaScript programs. Recently, many newly introduced devices are adopting 64-bit CPUs instead of 32-bit and Just-in-time compilers for 64-bit CPU are slowly being introduced in JavaScript engines. However, there are many inefficiencies in the currently available Just-in-time compilers for 64-bit devices. Especially, the size of code is significantly increased compared to 32-bit devices, mainly due to 64-bit wide addresses in 64-bit devices. In this paper, we are going to address the inefficiencies introduced by 64-bit wide addresses and values in the Just-in-time compiler for the V8 JavaScript engine and propose more efficient ways of generating constant values and addresses to reduce the size of code. We implemented the proposed optimization in the V8 JavaScript engine and measured the size of code as well as performance improvements with Octane and SunSpider benchmarks. We observed a 3.6% performance gain and 0.7% code size reduction in Octane and a 0.32% performance gain and 2.8% code size reduction in SunSpider.

• International journal of advanced smart convergence
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• v.11 no.4
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• pp.96-103
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• 2022

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm². In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.5 s.335
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• pp.47-54
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• 2005

This paper proposes and analyzes a Tag Anti-collision algorithm in RFID system. We mathematically compare the performance of the proposed algorithm with existing binary algorithms(binary search algorithm, slotted binary tree algorithm using time slot, and bit-by-bit binary tree algorithm proposed by Auto-ID center). We also validated analytic results using OPNET simulation. Based on analytic result, comparing the proposed Improved bit-by-bit binary tree algerian with bit-by-bit binary tree algorithm which is the best of existing algorithms, the performance of Improved bit-by-bit binary tree algorithm is about $304\%$ higher when the number of tags is 20, and $839\%$ higher when the number of tags is 200.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.8
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• pp.55-62
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• 2004

This paper proposes and analyzes two anti-collision algorithms in Ubiquitous ID system. We mathematically compares the performance of the proposed algorithms with that of binary search algorithm slotted binary tree algorithm using time slot, and bit-by-bit binary tree algorithm proposed by Auto-ID center. We also validated analytic results using OPNET simulation. Based on analytic result comparing the proposed Modified bit-by-bit binary tree algorithm with bit-by-bit binary tree algorithm which is the best of existing algorithms, the performance of Modified bit-by-bit binary tree algorithm is about 5% higher when the number of tags is 20, and 100% higher when the number of tags is 200. Furthermore, the performance of proposed Enhanced bit-by-bit binary tree algorithm is about 335％ and 145% higher than Modified bit-by-bit binary tree algorithm for 20 and 200 tags respectively.

• The Journal of the Korea Contents Association
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• v.11 no.8
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• pp.459-467
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• 2011

BIS(Bus Information Systems) supplies the bus arrived time information for users in using BIT(Bus Information Terminal) installed on the bus stop. BIT is the device using peoples directly. So, BIT need a quick response when it flew. These are an important factor in the strategy of the BIS maintenance. BIT need a maintenance cost to operate smoothly. So, Suppose that commercial advertisement can be displayed on BIT screen in this study. And we researched an advertisement rates of the optimum level in using Contingent Valuation Method. In addition, we analyzed a characteristic of user's depending on each time using multinomial Logit Modeling method, and studied for BIT operation and ad. displaying strategy considered user's sex, ages and using times.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.724-730
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• 2017

SpaceWire invented for spacecrafts has Time-Code defined for time synchronization over SpaceWire network. A Time-Code suffers transmission delay of 14[bit-period] and jitter up to 10[bit-period] whenever it passes through a SpaceWire link, which is the primary cause of time synchronization error. This work presents a simple method to improve the time synchronization which uses two extended Time-Codes. Nodes on a SpaceWire network can find how much delay and jitter a received Time-Code has suffered while it passes through the network, and they can correct time synchronization error with this information. The proposed method was validated in a simulation environment developed based on OMNeT++. The simulation result showed that time synchronization error less than a few bit-periods can be achieved. The proposed method is cost effective and suitable for small-scale SpaceWire network systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.225-228
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• 2012

In this paper, a 10-bit digital-to-analog converter (DAC) with small area is proposed. The 10-bit DAC consists of a 8-bit decoder, a 2-bit time-interpolator, and a buffer amplifier. The proposed time-interpolation is achieved by controlling the charging time through a low-pass filter composed of a resistor and a capacitor. To implement the accurate time-interpolator, a control pulse generator using a replica circuit is proposed to minimize the effect of the process variation. The proposed 10-bit Time-Interpolation DAC occupies 61 % of the conventional 10-bit resistor-string DAC. The proposed DAC is designed using a $0.35{\mu}m$ CMOS process with a 3.3 V supply. The simulated DNL and INL are +0.15/-0.21 LSB and +0.15/-0.16 LSB, respectively.

• Speech Sciences
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• v.10 no.2
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• pp.57-64
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• 2003

The cepstrum coefficients are the most popular feature for speech recognition or speaker recognition. The cepstrum coefficients are also used for speech synthesis and speech coding but has major drawback of long processing time. In this paper, we proposed a new method that can reduce the processing time of FFT cepstrum analysis. We use the normal ordered inputs for FFT function and the bit-reversed inputs for IFFT function. Therefore we can omit the bit-reversing process and reduce the processing time of FFT ceptrum analysis.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.82-84
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• 2001

Real-Time Linux는 기존의 Linux에 실시간 기능을 추가한 것으로서, 태스크 스케줄링 방법은 우선순위 기반의 스케줄링 방법을 사용한다. 그러나, 태스크의 개수가 많아지면 가장 높은 우선순위의 태스크를 찾는데 걸리는 시간이 태스크 개수에 비례해서 많이 걸린다. 이러한 이유로 태스크의 개수가 제한적일 수밖에 없다. 본 논문에서는 우선순위별로 서로 다른 목록을 유지하고, Bit Masking 기법을 사용함으로써 가장 높은 우선순위 태스크를 선택하는데 걸리는 시간을 상수시간으로 줄이고 각 태스크들의 시그널을 처리하는 부분을 좀더 효율적으로 처리하도록 함으로써 Real-Time Linux의 실시간 스케줄링 기능을 개선하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.2
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• pp.306-317
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• 1997

This ppaer presents a bit-rate conversion system for efficient communications between 3 channel CVSD systems with different bit-rates. The proposed conversion system is implemented in the digital domain and specially, the conversion problem between 32 Kbps and 16 Kbps CVSD systems is studied. The conventional conversion system implemented in the analog domain allows signals to be easily degraded by external noises. To overcome this problem, a digital CVSD bit-rate conversion system robust to external noises is developed. the new systemdecodes CVSD bit sequences and converts sampling rates of decoded signals, then encodes signals at target bit-rates. Since linear phase property does not matter in this application, instead of FIR filters a IIR filter is employed to reduce the system complexity. Therefore, a 3 channel digital CVSD bit-rate conversion system was successfully real-time implemented using a general purpose DSP. In addition, conversion problems with unkown time constants were experimented and good experimental results were obtained.