• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.32-39
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• 1996

Hybrid decision decoding for the extended hamming codes without retransmission, which is a combination of hard and soft decision decoding, is proposed and its performance is analyzed in this paper. As results, hybsrid decision decoding shows a little bit higher residual bit error rate than soft decision decoding. However, as the size of the extended hamming code increases, the difference of th enumber of comparisons increases further. In addition, hybrid decision decoding shows almost same residual bit error rate as hard decision decoding with retrassmission and shows much lower residual bit error rate than hard decision decoding without retransmission.

• Journal of Broadcast Engineering
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• v.22 no.1
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• pp.42-50
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• 2017

A Bit-depth expansion is a method to increase the number of bit. It is getting important as the needs of HDR (High Dynamic Range) display or resolution of display have been increased because the level of luminance or expressiveness of color is proportional to the number of bit in the display. In this paper, we present effective bit-depth expansion algorithm for conventional standard 8 bit-depth content to display in high bit-depth device (10 bits). Proposed method shows better result comparing with recently developed methods in quantitative (PSNR) with low complexity. The proposed method shows 1db higher in PSNR measurement with 40 times faster in computational time.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.7
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• pp.1-9
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• 1992

In this thesis, the trellis detection scheme is proposed to improve the error performance of the noncoherent detection in the TFM system. Trellis detection takes advantage of the trellis property of TFM-encoded signals. The trellis property is created by giving correlations among adjacent TFM-encoded signals at the transmitter. The performance of the trellis detection scheme is analyzed by means of the Bernoulli trials with the average symbol error probability, and is compared to that of the bit-by-bit detection scheme. As a result,when the SNR is below 20 dB in the Rayleigh fading and AWGN channel, the trellis detection is inferior to the bit-by-bit detections. But when SNR is above 20 dB, the trellis detection is superior to the bit-by-bit detection, and its performance enhancement is better as the SNR increases.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.161-166
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• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.1177-1183
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• 1995

This paper proposes a new modulation scheme of $\pi$/4-DQPSK with stepped phase for a frequency selective fading channel. In the proposed modulation scheme, the phase of transmitted signal is shifted in the mid of a symbol duration in order to reduce the effect of multipath delay spread. It reduces the irreducible error of $\pi$/4-DQPSK over a frequency selective fading channel. It is shown that $\pi$/4-DQPSK with stepped phase achieves smaller average bit error probability than regular $\pi$/4- DQPSK by simulation. The former achieves much smaller average bit error probability than the latter for small TEX>${\tau}/T_{s}$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.220-228
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• 1995

An optimized 4-stage 12-bit pipelined CMOS analog-to-digital converter (ADC) architecture is proposed to obtain high linearity and high yield. The ADC based on a multiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted-capacitor (BWC) array in the front-end stage and a unit-capacitor (UC) array in the back-end stages to improve integral nonlinearity (INL) and differential nonlinearity (DNL) simultaneously whil maintaining high yield. A digital-domain nonlinear error calibration technique is applied in the first stage of the ADC to improve its accuracy to 12-bit level. The largest DNL error in the mid-point code of the ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is simulated to prove the effectiveness of the proposed ADC architecture.

• The Journal of the Acoustical Society of Korea
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• v.24 no.2E
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• pp.61-66
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• 2005

Experimental work in underwater acoustic communications using passive phase conjugation has shown that the demodulation error depends on the relative drift rate between the source and receiver [Rouseff et al., IEEE J. Oceanic Eng. 26, 821-831 (2001)]. The observed effect involves the mismatch between the initial impulse response and the subsequent response after the source or receiver has changed locations. In the present work, the effect of drifting source is analyzed by numerical simulations and compared to the experimental results. The communications bit error rate is qualified as a function of drift rate, drifting direction, and source-receiver range.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.2
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• pp.193-199
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• 2017

In this paper, we proposed an architecture of error detection in $Z_N$ operations using $Z_{(2^r-1)N}$. The error detection can be simply constructed in hardware. The hardware overheads are only 50% and 1% with respectively space and time complexity. The architecture is very efficient because it is detection 99% for 1 bit fault. For 2 bit fault, it is detection 99% and 50% with respective r=2 and r=3.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.484-490
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• 1990

In speech coding scheme, because information bits have different error sensitivities over channel errors, the channel coder for combining with speech coding should be realized by the variable coding rate considering the bit importance of speech information bits. In realizing the 4 kbps channel coder for 12kbps speech, this paper have chosen the channel coding method by analyzing the hard-decision post-decoding error rate of RCPC(Rate Compatible Punctured Convolutional) codes and bit error sensitivity of 12 kbps speech. Under the coherent QPSK and Rayleigh fading channel, the performance analysis has showed that 10dB gain was obtained in speech SEGSNR by 4-level uneuqal error protection, which was compared with the caseof no channel coding at 7dB channel SNR.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.104-110
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• 2006

The advantage of the DSM which employ multi-bit quantizer is the increased SNR at the modulator's output. Typically 6 dB improvement is effected for every one additional bit. But multi-bit quantizer evidently requires multi-bit DAC in the feedback loop. The integral linearity error of the feedback DAC has direct impact upon the system performance and degraded SNR of the system. In order to mitigate the negative impact the DAC has on the system performance, many DEM(Dynamic Element Matching) schemes has been proposed. Among the proposed schemes, four schemes(DER,CLA,ILA,DWA) are explained and its performance has been compared. DWA(Data Weighted Averaging) method shows the best performance of the all.