• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.9
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• pp.531-538
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• 2005

This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.311-317
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• 2011

Recently, RFID is substituted for bar codes according to advance in the ubiquitous computing environments, but the RFID system has several problems such as security and privacy because it uses radio frequencies. Firstly, unauthorized reader can easily read the ID information of any Tag. Secondly, Attacker can easily fake the legitimate reader using the collected Tag ID information,such as the any legitimate tag. This paper proposed improved RFID authentication protocol based on SSG. SSG is organized only one LFSR and selection logic. Thus SSG is suitable for implementation of hardware logic in system with extremely limited resources such as RFID tag and it has resistance to known various attacks because of output bit stream for the use as pseudorandom generator. The proposed protocol is secure and effective because it is based on SSG.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.209-212
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• 2003

본 논문에서는 PC 환경에서 지상파 디지털 멀티미디어 방송(Digital Multimedia Broadcasting, DMB)을 수신할 수 있는 PC 기반 지상파 DMB 수신기용 백엔드 시스템 개발에 대해 서술한다. 지상파 DMB는 기존의 지상파 아날로그 또는 디지털 TV에 비해 탁월한 이동 수신 성능을 보인다. 본 논문에서는 국내 지상파 DMB 표준안에 부합하는 수신기의 백엔드 (back-end)를 PC 환경에서 소프트웨어로 구현하였다. 지상파 DMB는 유럽의 디지털 오디오 방송(Digital Audio Broadcasting, DAB) 표준인 EUREKA-147을 기반으로 MPEG-4 표준에 의한 멀티미디어 서비스를 제공한다. 지상파 DMB의 멀티미디어 서비스는 MPEG-4 AVC(Advance Video Coding) 압축 비디오와 BSAC(Bit Slice Arithmetic Coding) 압축 오디오를 MPEG-4 시스템의 SL(Sync Layer) 표준으로 패킷화 후 MPEG-2 TS(Transport Stream)에 실어 DAB의 스티림 모드를 통해 전송하는 방식을 사용한다. 본 논문에서는, 지상파 DMB 수신을 위한 프론트엔드(front-end)는 외장형 기기를 이용하고, 이로부터 USB 인터페이스를 통해 기저대역 다중화 스트림을 PC 상으로 업로드한 뒤, 소프트웨어에 의해 역다중화하고 압축을 푼 후, 오디오와 비디오를 재생하는 지상파 DMB 백엔드 시스템을 구현하고 이를 검증하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1285-1288
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• 2002

Bluetooth wireless technology is a publicly available specification proposed for Radio Frequency (RF) communication for short-range and point-to- multipoint voice and data transfer. It operates in the 2.4GHz ISM(Industrial, Scientific and Medical) band and offers the potential for low-cost, broadband wireless access for various mobile and portable devices at range of about 10 meters. In this paper, we describe the structure and the test results of the bluetooth baseband module we have developed. This module was developed based on IP reuse. So Interface of each module such as link controller UART, and audio CODEC is designed based on ARM7 comfortable processor. We also considered various interfaces of related external chips. The fully synthesizable baseband module was fabricated in a $0.25{\mu}m$ CMOS technology occupying $2.79{\times}2.8mm^2$ area including the ARM TDMI processor. And a FPGA implementation of this module is tested for file and bit-stream transfers between PCs.

• Journal of the Korea Computer Industry Society
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• v.2 no.7
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• pp.997-1014
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• 2001

In this paper, we propose a method for dynamic selection of unrestricted motion vector(UMV) or default prediction mode(DPM) in H.263 bit stream. For this, we use the error of compensated image and the magnitude of motion vector. In the proposed strategy, the UMV mode is dynamically applied in a frame according to average magnitude of motion vector and error of compensated image. This scheme has improved the quality of image compared to the fixed mode UMV or DPM only. Number of searching points are greatly reduced when comparing to UMV. The Proposed method is more profitable to long video sequences having camera movement locally.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.141-144
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• 2008

IPTV, VOD와 같은 스트리밍 서비스와 유료 케이블 TV 방송 채널, 유료 위성방송 채널 등에는 반드시 제한 수신 시스템(Conditional Access System, CAS)이 필요하다. CAS시스템은 인증 받은 사용자에게는 깨끗한 화면을 보여주어야 하고 인증 받지 않은 사용자에게는 정상적으로 화면을 즐길 수 없도록 하여야 한다. 이러한 환경을 만들기 위하여 추가비용이 적은 알고리즘이 필요한데 그 방법으로 암호화를 제안한다. 본 논문에서는 CAS 등의 인증시스템을 위하여 H.264 영상의 선택적 암호화를 구현하였다. 제안하는 방법은 여러 가지 포맷으로 된 콘텐츠를 트랜스코딩하여 YUV 형식으로 변환한 뒤, 이것을 H.264 코덱을 이용하여 압축한 다음 필요에 따라 특정한 부분을 암호화하는 것이다. 실험을 통하여 암호화 키가 없는 미 인증 사용자는 영상을 제대로 볼 수 없었고 암호화의 강도를 강하게 할 경우 재생은 되지만 영상의 확인이 불가능함을 확인하였다. 또한 300프레임의 영상을 암호화 하는데 평균 71.3초가 걸려 속도 역시 빠름을 확인하였다. 제안하는 내용은 IPTV, VOD와 같은 스트리밍 서비스에서의 사용자 인증 및 저작권 보호 등의 분야에 유용하게 사용될 것이다.

• The Journal of the Acoustical Society of Korea
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• v.26 no.6
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• pp.269-275
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• 2007

Pervasive Multi-channel audio systems are being realized due to advances in digital technology. This paper proposes an efficient system that serially connects individual speakers with bidirectional digital communication capability by means of SoC design. In particular, each speaker can identify the bit stream assigned to the speaker and convert it into analog audio. Furthermore, the speaker can self-diagnose the speaker functionality by utilizing the designed capability to measure frequencies of various square wave test signals. The proposed system running on 200MHz clock yielded restoration of analog output signal with latency of only $500{\mu}s$ compared to directly driving the speakers in a traditional way.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.2
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• pp.311-326
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• 2018

This paper has experimented using News sample video with QCIF ($176{\times}144$) resolution in JM v10.2 code of H.264/AVC-MPEG. The region of interest (ROI) to be encrypted occurred the drift by unnecessarily referring to each frame continuously in accordance with the characteristics of the motion prediction and compensation of the H.264 standard. In order to mitigate the drift, the latest related research method of re-inserting encrypted I-picture into a certain period leads to an increase in the amount of additional computation that becomes the factor increasing the bit-rate overhead of the entire video. Therefore, the reference search range of the block and the frame in the ROI to be encrypted is restricted in the motion prediction and compensation for each frame, and the reference search range in the non-ROI not to be encrypted is not restricted to maintain the normal encoding efficiency. In this way, after encoding the video with restricted reference search range, this article proposes a method of RC4 bit-stream encryption for the ROI such as the face to be able to identify in order to protect personal information in the video. Also, it is compared and analyzed the experimental results after implementing the unencrypted original video, the latest related research method, and the proposed method in the condition of the same environment. In contrast to the latest related research method, the bit-rate overhead of the proposed method is 2.35% higher than that of the original video and 14.93% lower than that of the latest related method, while mitigating temporal drift through the proposed method. These improved results have verified by experiments of this study.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.76-84
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• 1999

EZW proposed by Shapiro is based on a zerotree constructed in a way that a parent coefficient in a subband is related to four child coefficients in the next finer subband of similar orientation. This fixed treeing based on 1-to-4 parent-child is suitable to exploti hierachical correlations among subbands but not to exploit spatial correlations within a subband. A new treeing by Joo, et al. is suggested to simulatneously exploit those two correlatins by extending parent-child relationship in a flexible way. The flexible treeing leads to increasing the number of symbols and lowering entorpy comparing to the fixed treeing, and therefore a better compression can be resulted. In this paper, we suggest two techniques to suppress the increasing of symbols. First, a probing bit is generated to avoid redundant scan for insignivicant coefficients. Second, since all subbands do not always require the same kind of symbol-set, produced symbols are re-symbolized into binary codes according to a pre-defined procedure. Owing to those techniques, all symbols are generated as binary codes. The binary symbols can be entropy-coded by an adaptive arithmetic coding. Moerover, the binary symbol stream can give comparatively good performances without help of additional entropy coding. Our proposed coding scheme is suggested in two modes: binary coding mode and arithmetic coding mode. We evaluate the effectivenessof our modifications by comparing with the original EZW.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.