• Journal of Internet Computing and Services
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• v.17 no.4
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• pp.19-26
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• 2016

In this paper, the dynamic buffering based smart OTT platform was proposed, and analyzed for adaptive bit-rate video delivery with the optimization of HLS (HTTP Live Streaming). This platform consists of the software platform between sever and client which detects the bandwidth capacity, and adjusts the quality of the streaming for multiple bit-rates resolutions. In order to apply adaptive buffering, two buffers are added to the basic HLS player, and each buffer is responsible for constantly buffering a previous and the next channels relative to the current channel. This adaptive transmitting with smart OTT platform is superior to delivering a static video file at a single buffering, because the video stream of adaptive double buffers can be switched streaming according to client's available network speed. As a result, this proposed smart OTT can be cooperated to the application of HLS server with segmented H.265 MPEG-2 TS video & m3u8 files with its information based on the optimized transmission channel state of live and VOD, and applied to PLC transmission, too.

• Journal of Korea Multimedia Society
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• v.13 no.4
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• pp.560-574
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• 2010

Recently, many people can easily contact video telephony service through the mobile terminal owing to the commercialization of 3G communication technology. However, the quality of the serviced video telephony has been not good yet by the actual mobile restrictions. For solving quality problems, this paper presents the design of the object-based video CODEC using hybrid transform in mobile video telephony. The proposed design firstly segment each frame into a significant object and an insignificant object. The proposed design is to improve the quality of a significant object by limiting the bit rate of a insignificant object. Thus, we compress a significant object with high quality and low compression ratio and compress an insignificant object with low quality and high compression ratio. Furthermore, we control the bit rate of the video stream in the limited bandwidth by adjusting the compression ratio of each object. From experimental results, we confirmed that our method has more higher quality than methods in the conventional CODECs at the significant region on the same bit rate.

• Journal of Broadcast Engineering
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• v.6 no.2
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• pp.121-130
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• 2001

We propose an efficient DCT-domain video transcoding algorithm for flexible for bit-rate video communications. Video transcoding provides communication fiexibility by adaptively changing the bit-rate of compressed bit stream. During the transcoding process, adrift error is unavoidable because of the difference between reference images in the series of encoding and decoding. For solving the drift error problem, cascade pixel-domain transcoder (CPDT) has been proposed. CPDT, however, requires highly complex hardware and heavy computational overhead. In this paper we propose a DCT-domain transcoding technique, which enables efficient transcoding without any drift error. The proposed cascade DCT-domain transcoder (CDDT) is realized by new motion compensation and down-sampling methods in the DCT-domain.

• Journal of KIISE:Information Networking
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• v.30 no.6
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• pp.695-704
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• 2003

A wavelet-based video stream is more susceptible to the network transmission errors than DCT-based video. This is because bit-errors in a subband of a video frame affect not only the other subbands within the current frame but also the subsequent frames. In this paper, we propose a video source coding scheme called IPC(Intra Prediction Coding) scheme in order to reduce the error propagation to the subsequent frames. In the proposed scheme, a subband except LL subband in the current frame refers to the lower-level subband within the same frame. This reduces the error propagation to subsequent frames. We evaluated the performance of our proposed scheme in the simulated wireless network environment. As a result of tests, it was shown that the proposed algorithm shows better performance than MRME in a heavy motion image sequence while IPC outperforms MRME at a high bit-rate in small motion image sequence.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.778-781
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• 2007

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture protype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.

• The KIPS Transactions:PartC
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• v.11C no.6 s.95
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• pp.747-754
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• 2004

Today, wireless LANs are widely deployed in various places such as corporate office conference rooms, industrial warehouses, Internet-ready classrooms, etc. However, new concerns have been raised regarding suity. Currently, both virtual private network(VPN) and WEP are used together as a strong authentication mechanism. While security is increased by using VPN and WEP together, unnecessary redundancy occurs causing power consumption increase and authentication speed decrease in the authentication process. In this paper a new synchronization protocol for authentication is proposed which allows simple authentication, minimal power consumption at the mobile station, and high utilization of authentication stream. This is achieved by using one bit per a frame authentication, while main authentication process including synchronization is handled by access points. Computer simulation reveals that the proposed scheme significantly improves the authentication efficiency in terms of the number of authenticated frames and authentication speed compared with an earlier protocol employing a similar authentication approach.

• The KIPS Transactions:PartC
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• v.11C no.7 s.96
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• pp.1009-1022
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• 2004

Smoothing is a transmission plan where variable rate video data is converted to a constant bit rate stream. Among them are CHA, MCBA. MVBA, e-PCRTT and others. E-PCRTT algorithm, which was improved from PCRTT, restricts the number of rate changes with fixed-size run. This causes unnecessary rate changes and may not guarantee QoS when buffer size is small. In this paper. a smoothing algorithm is pro-posed, where the number of rate changes are not limited and the size of run can be flexible, in order to overcome the shortcomings of e-PCRTT. Experiments demonstrated that the proposed algorithm such as e-PCRTT. In order to show the performance, var-ious evaluation factors were used such as the nember of rate changes, buffer size to maintain QoS, and so on.

• Journal of Broadcast Engineering
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• v.13 no.5
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• pp.707-718
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• 2008

We derive a modified version of the cubic convolution scaler to enlarge or reduce the size of digital image with arbitrary ratio. To enhance the edge information of the scaled image and to obtain a high-quality scaled image, the proposed scaler is applied along the direction of an edge. Since interpolation along the direction of an edge has to process nonuniformly sampled data, the kernel of the cubic convolution scaler is modified to interpolate the data. The proposed scaling scheme can be used to resize pictures in various formats in a transcoding system that transforms a bit stream compressed at one bit rate into one compressed at another bit rate. In many applications, such as transcoders, the resolution conversion is very important for changing the image size while maintaining high quality of the scaled image. We show experimental results that demonstrate the effectiveness of the proposed interpolation method. The proposed scheme provides clearer edges, without artifacts, in the resized image than do conventional schemes. The algorithm exhibits significant improvement in the minimization of information loss when compared with the conventional interpolation algorithms.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.10
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• pp.1065-1074
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• 2008

T-DMB(Terrestrial Digital Multimedia Broadcasting) system, is based on the Eureka-147 standard, provides various multimedia data services. However T-DMB system needs upgrades for more various services and better services. Therefore, we proposed advanced T-DMB system using unequal error protection system and hierarchical modulation in this paper while maintaing backward compatibility. And we simulated various bit split methods and double binary turbo code of DVB-RCS standard as method of LP data stream for additional service of advanced T-DMB. As the simulation results, double binary turbo code of proposed advanced T-DMB system have each coding gain of over 2 dB compared to conventional T-DMB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.65-70
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• 2008

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b${\times}$32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.