• Title/Summary/Keyword: Bit Map

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Redundancy Analysis Simulation for EDS Process (EDS 공정에서 Redundancy Analysis 시뮬레이션)

  • 서준호;이칠기
    • Journal of the Korea Society for Simulation
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    • v.11 no.3
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    • pp.49-58
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    • 2002
  • It takes 2 or 3 months to manufacture memory device. Defect has to exist owing to hundreds of processes. If there are too many defects, the memory has to be rejected. But if there are a few defects, it will be more efficient and cost reducing for the company to use it by repairing. Therefore, laser-repair process is needed for such a reason and redundancy analysis is needed to establish correct target of laser-repair process. The equipment development company had provided the redundancy analysis and each development company had developed and provided separately. So, to analyze the similar type of defects, redundancy analysis time can be very different by the manufacture. The purpose of this research is to strengthen the competitive price and to apply correlation concept in business for reducing the redundancy analysis time to repair the defects

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Recovering from Bit Errors in Scalar-Quantized Discrete Wavelet (양자화된 이산 웨이블릿 변환 영상에서의 비트 에러 복원)

  • 최승규;이득재;장은영;배철수
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.05a
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    • pp.594-597
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    • 2002
  • In this paper we study the effects of transmission noise on fixed-length coded wavelet coefficients. We use a posteriori detectors which include inter-bitplane information and determine which transmitted codeword was most likely corrupted into a received erroneous codeword We present a simple method of recovering from these errors once detected and demonstrate our restoration methodology on scalar-quantized wavelet coefficients that have been transmitted across a binary symmetric channel.

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A Local Weight Learning Neural Network Architecture for Fast and Accurate Mapping (빠르고 정확한 변환을 위한 국부 가중치 학습 신경회로)

  • 이인숙;오세영
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.28B no.9
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    • pp.739-746
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    • 1991
  • This paper develops a modified multilayer perceptron architecture which speeds up learning as well as the net's mapping accuracy. In Phase I, a cluster partitioning algorithm like the Kohonen's self-organizing feature map or the leader clustering algorithm is used as the front end that determines the cluster to which the input data belongs. In Phase II, this cluster selects a subset of the hidden layer nodes that combines the input and outputs nodes into a subnet of the full scale backpropagation network. The proposed net has been applied to two mapping problems, one rather smooth and the other highly nonlinear. Namely, the inverse kinematic problem for a 3-link robot manipulator and the 5-bit parity mapping have been chosen as examples. The results demonstrate the proposed net's superior accuracy and convergence properties over the original backpropagation network or its existing improvement techniques.

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A Study on the Construction of a Document Input/Output system (문서 입출력 시스템의 구성에 관한 연구)

  • 함영국;도상윤;정홍규;김우성;박래홍;이창범;김상중
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.29B no.10
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    • pp.100-112
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    • 1992
  • In this paper, an integrated document input/output system is developed which constructs the graphic document from a text file, converts the document into encoded facsimile data, and also recognizes printed/handwritten alphanumerics and Korean characters in a facsimile or graphic document. For an output system, we develop the method which generates bit-map patterns from the document consisting of the KSC5601 and ASCII codes. The binary graphic image, if necessary, is encoded by the G3 coding scheme for facsimile transmission. For a user friendly input system for documents consisting of alphanumerics and Korean characters obtained from a facsimile or scanner, we propose a document recognition algirithm utilizing several special features(partial projection, cross point, and distance features) and the membership function of the fuzzy set theory. In summary, we develop an integrated document input/output system and its performance is demonstrated via computer simulation.

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Scalable Coding of Depth Images with Synthesis-Guided Edge Detection

  • Zhao, Lijun;Wang, Anhong;Zeng, Bing;Jin, Jian
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.9 no.10
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    • pp.4108-4125
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    • 2015
  • This paper presents a scalable coding method for depth images by considering the quality of synthesized images in virtual views. First, we design a new edge detection algorithm that is based on calculating the depth difference between two neighboring pixels within the depth map. By choosing different thresholds, this algorithm generates a scalable bit stream that puts larger depth differences in front, followed by smaller depth differences. A scalable scheme is also designed for coding depth pixels through a layered sampling structure. At the receiver side, the full-resolution depth image is reconstructed from the received bits by solving a partial-differential-equation (PDE). Experimental results show that the proposed method improves the rate-distortion performance of synthesized images at virtual views and achieves better visual quality.

PRaCto: Pseudo Random bit generator for Cryptographic application

  • Raza, Saiyma Fatima;Satpute, Vishal R
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.12
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    • pp.6161-6176
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    • 2018
  • Pseudorandom numbers are useful in cryptographic operations for using as nonce, initial vector, secret key, etc. Security of the cryptosystem relies on the secret key parameters, so a good pseudorandom number is needed. In this paper, we have proposed a new approach for generation of pseudorandom number. This method uses the three dimensional combinational puzzle Rubik Cube for generation of random numbers. The number of possible combinations of the cube approximates to 43 quintillion. The large possible combination of the cube increases the complexity of brute force attack on the generator. The generator uses cryptographic hash function. Chaotic map is being employed for increasing random behavior. The pseudorandom sequence generated can be used for cryptographic applications. The generated sequences are tested for randomness using NIST Statistical Test Suite and other testing methods. The result of the tests and analysis proves that the generated sequences are random.

An Efficient Data Centric Storage Scheme with Non-uniformed Density of Wireless Sensor Networks (센서의 불균일한 배포밀도를 고려한 효율적인 데이터 중심 저장기법)

  • Seong, dong-ook;Lee, seok-jae;Song, seok-il;Yoo, jae-soo
    • Proceedings of the Korea Contents Association Conference
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    • 2007.11a
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    • pp.135-139
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    • 2007
  • Recently Data Centric Storage (DCS) schemes are variously studied for several applications (e.g. natural environment investigation, military application systems and environmental changes monitoring). In DCS scheme, data is stored at nodes within the network by name. There are several drawbacks in the existing schemes. The first is the inefficiency of the range query processing on not considered the locality of store point. the second is the non-homogeneity of store load of each sensors in case of the sensor distribution density is non-uniformed. In this paper, we propose a novel data centric storage scheme with the sensor distribution density which satisfied with the locality of data store location. This scheme divides whole sensor network area using grid and distributes the density bit map witch consist of the sensor density information of each cell. sensors use the density bit map for storing and searching the data. We evaluate our scheme with existing schemes. As a result, we show improved load balancing and more efficient range query processing than existing schemes in environment which sensors are distributed non-uniform.

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A study on the image transmission through CDMA (CDMA 채널을 통한 영상 전송에 대한 연구)

  • 허도근;김용욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.11
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    • pp.2543-2551
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    • 1997
  • This paper proposes a compression technique of image data, a variable length PN code and channel models which are required in CDMA communication system. It also analyzes their performances. Original images is compressed by 2-D DCT and its coefficients are quantized by optimal quantizer at compression rate 0.84bit/pel. Channel model 1 and 2 which are composed of 5 and 4 channels respectively are employed to be used in CDMA. Such a situation forces us to empoly variable length PN code, such as Chebyshev map for spread spectrum system. When average PN code length of model 1 and 2 is 44.4 and 26.7 chips respectively, the received image through these models under Gaussian noise with variance 1.75 is visually of the same quality as the transmitting image. Thus, the model 2 appears to be better in channel efficiency, comparing with channel model 1 and channel model which uses fixed length PN code.

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Design of a systolic radix-4 finite-field multiplier for the elliptic curve cryptography (타원곡선 암호를 위한 시스톨릭 Radix-4 유한체 곱셈기 설계)

  • Park Tae-Geun;Kim Ju-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.3 s.345
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    • pp.40-47
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    • 2006
  • The finite-field multiplication can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-parallel, bit-serial and systolic multipliers, the proposed multiplier has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

Efficient systolic VLSI architecture for division in $GF(2^m)$ ($GF(2^m)$ 상에서의 나눗셈연산을 위한 효율적인 시스톨릭 VLSI 구조)

  • Kim, Ju-Young;Park, Tae-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.3 s.357
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    • pp.35-42
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    • 2007
  • The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.