• 대한전자공학회논문지
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• 제26권7호
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• pp.125-131
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• 1989

본 논문에서는 기존의 BTC 방법을 개선한 새로운 ABTC(adaptive block truncation coding) 방법을 제안하였다. ABTC 알고리듬은 화상데이터의 부분적인 특성에 따라 압축방식을 선택적으로 적용함으로써 높은 압축률로 우수한 화질의 재생화면을 얻을 수 있다. ABTC 화상압축방식은 압축 알고리듬이 간단하면서도 높은 압축률을 얻을 수 있는 특징이 있다. 이 알고리듬을 사용하면 칼라화상을 1.0(bit/pel)에서 2.26(bit/pel)의 데이터 부호율 범위내에서 임의로 코딩할 수 있으며 원래의 화상에 비해 화질의 큰 손상없이 높은 압축률 $1.3{\sim}1.5bit/pel$을 얻을 수 있다.

• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.310-318
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• 2016

Emerging technologies such as the Internet of Things (IoT) and the Advanced Driver Assistant System (ADAS) often have image transmission functions with tough constraints, like low power and/or low delay, which require that they adopt line-based, low memory compression methods instead of existing frame-based image compression standards. Bit rate control in the conventional frame-based compression systems requires a lot of hardware resources when the scope of handled data falls at the frame level. On the other hand, attempts to reduce the heavy hardware resource requirement by focusing on line-level processing yield uneven image quality through the frame. In this paper, we propose a bit rate control that maintains consistency in image quality through the frame and improves the legibility of text regions. To find the line characteristics, the proposed bit rate control tests each line for ease of compression and the existence of text. Experiments on the proposed bit rate control show peak signal-to-noise ratios (PSNRs) similar to those of conventional bit rate controls, but with the use of significantly fewer hardware resources.

• Journal of Communications and Networks
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• 제10권1호
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• pp.79-88
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• 2008

In this paper, we propose efficient peer assignment algorithms for low-latency transmission of scalable coded images in peer-to-peer networks, in which peers may dynamically join and leave the networks. The objective of our algorithm is to minimize the transmission time of a requested image that is scalable coded. When an image is scalable coded in different bit rates, the bit stream encoded in a lower bit rate is a prefix subset of the one encoded in a higher bit rate. Therefore, a peer with the same requested image coded in any bit rate, even when it is different from the requested rate, may work as a supplying peer. As a result, when a scalable coded image is requested, more supplying peers can be found in peer-to-peer networks to help with the transfer. However, the set of supplying peers is not static during transmission, as the peers in this set may leave the network or finish their transmission at different times. The proposed peer assignment algorithms have taken into account the above constraints. In this paper, we first prove the existence of an optimal peer assignment solution for a simple identity permutation function, and then formulate peer assignment with this identity permutation as a mixed-integer programming problem. Next, we discuss how to address the problem of dynamic peer departures during image transmission. Finally, we carry out experiments to evaluate the performance of proposed peer assignment algorithms.

• 한국통신학회논문지
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• 제25권6B호
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• pp.1002-1011
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• 2000

본 논문에서는 $2{\times}2$ DCT(Discrete Cosine Transform)와 임베디드 제로 트리(Embedded Zero Tree)를 이용한 공간(Spatial) 및 비트율(bit-rate) 계위(scalability)를 갖는 순차 영상 전송 기법을 제안한다. 제안된 방법은 영상의 다해상도 표현을 위해 $2{\times}2$ DCT를 사용하여 고차 웨이브렛 필터에 비해 계산량이 많이 감소하여 실시간 응용에 적합하도록 하였으며, 공간과 비트율 계위를 동시에 가지도록 하여 수신자의 계위 요구에 적응적으로 대응하도록 하였다. 실험 결과 고차 웨이브렛 필터를 이용한 순차 영상 전송과 비교하여 계산량의 상당한 감소에도 불구하고 화질의 차이는 거의 인식할 수 없었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 컴퓨터소사이어티 추계학술대회논문집
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• pp.157-160
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• 2003

Recently, several steganographic algorithms for two-color binary images have been proposed. In this paper, we propose a steganographic algorithm which embeds a secret message into bitmap images and palette-based images. To embed a message, the suggested algorithm divides a bitmap image into bit-plane images from LSB-plane to MSB-plane for each pixel, and considers each bit-plane image as a binary one. The algorithm splits each bit-plane image into m$\times$n blocks. and embeds a r-bit(r=[log$_2$(mn+1]-1) message into the block. And our schemes embed a message to every bit-plane from LSB to MSB to maximize the amount of embedded message and to minimize the degradation. The schemes change at most two pixels in each block. Therefore, the maximal color changes of the new algorithm are much smaller than other bit-plane embedding schemes' such as the substantial substitution schemes.

• 한국산업정보학회:학술대회논문집
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• 한국산업정보학회 2007년도 춘계학술대회
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• pp.35-39
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• 2007

We applied digital image processing about BitMap file structure in this research and studied about digital communication system. digital record saving devices can express 'High' and 'Low' as all data. Only, digital technique that two expression methods is used into several expenditures. People and communication that are far away by development of digital technology, became smooth. We wished to make communication system taking advantage of digi-tech. This system was made for communication with disabled and normal person specially. To communication method that we are studied such BitMap file handling image communication system. The goal of this contribution is to present the overview of basic algorithms for image processing using BitMap.

• Journal of Platform Technology
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• 제6권4호
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• pp.26-33
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• 2018

In this paper, we propose an image retrieval algorithm for real-time processing and design it as hardware. The proposed method is based on the classification of BoWs(Bag of Words) algorithm and proposes an image search algorithm using bit stream. K-fold cross validation is used for the verification of the algorithm. Data is classified into seven classes, each class has seven images and a total of 49 images are tested. The test has two kinds of accuracy measurement and speed measurement. The accuracy of the image classification was 86.2% for the BoWs algorithm and 83.7% the proposed hardware-accelerated software implementation algorithm, and the BoWs algorithm was 2.5% higher. The image retrieval processing speed of BoWs is 7.89s and our algorithm is 1.55s. Our algorithm is 5.09 times faster than BoWs algorithm. The algorithm is largely divided into software and hardware parts. In the software structure, C-language is used. The Scale Invariant Feature Transform algorithm is used to extract feature points that are invariant to size and rotation from the image. Bit streams are generated from the extracted feature point. In the hardware architecture, the proposed image retrieval algorithm is written in Verilog HDL and designed and verified by FPGA and Design Compiler. The generated bit streams are stored, the clustering step is performed, and a searcher image databases or an input image databases are generated and matched. Using the proposed algorithm, we can improve convenience and satisfaction of the user in terms of speed if we search using database matching method which represents each object.

• 전자공학회논문지B
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• 제31B권4호
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• pp.30-39
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• 1994

A 1-chip high quality binarizing VLSI image processor (which has 8 bit ADC. 6 bit flash ADC, 15K standard cell, and 1K word ROM) based on 10 MIPS 16 bit DSP is implemented for FAX. This image processor(IP) performs image pre-processing. image quality improvement in copying and sending mode, and mixed image processing based on the fuzzy theory. And smoothing in sub-scan direction is applied for normal receiving mode data so the received data is enhanced like fine mode data. Each algorithm is processed with the same type of image processing window and 2-D image processing is implemented with a 1-D line buffer. The fabricated chip is applied to a FAX machine and image quality improvement is verified.

• 전자공학회논문지
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• 제50권11호
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• pp.64-69
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• 2013

본 논문에서는 10-bit 해상도의 Two-Step Single-Slope A/D 변환기를 이용한 고속 CMOS Image Sensor(CIS)를 제안하였다. 제안하는 A/D 변환기는 5-bit coarse ADC 와 6-bit fine ADC 로 구성되어 있으며, 기존의 Single-Slope A/D 변환기보다 10배 이상의 변환속도를 나타내었다. 또한 고속 동작에서 적은 노이즈 특성을 갖기 위해 Digital Correlated Double Sampling(D-CDS) 회로를 제안하였다. 설계된 A/D 변환기는 0.13um 1-poly 4-metal CIS 공정으로 제작되었으며 QVGA($320{\times}240$)급 해상도를 갖는다. 제작된 칩의 유효면적은 $5mm{\times}3mm$ 이며 3.3V 전원전압에서 약 35mW의 전력소모를 나타내었다. 변환속도는 10us 이었으며, 프레임율은 220 frames/s으로 측정되었다.

• 한국정보통신학회논문지
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• 제13권4호
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• pp.684-690
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• 2009

본 논문은 유사도를 이용한 비트플레인 기반의 스테가노그라피 방법을 제안하였다. 기존의 방법은 모든 비트플레인에 고정 임계값을 적용하므로 정보 삽입시 화질의 열화가 발생한다. 본 연구는 정보 삽입을 위해 커버 영상의 비트플레인에 블록 복잡도와 블록 유사도를 정의하고 가장 적합한 블록에 정보를 삽입하는 방법이다. 실험은 표준 이미지에 동일한 화질과 정보량을 삽입하고 이에 따른 삽입 용량과 화질을 비교하였다. 실험 결과, 제안한 방법이 기존의 방법보다 삽입 용량이 평균 6%의 정도가 증가되었고, 화질면에서는 평균 약 3.3dB이 향상되었다.