• 전자공학회논문지A
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• 제33A권2호
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• pp.32-39
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• 1996

Hybrid decision decoding for the extended hamming codes without retransmission, which is a combination of hard and soft decision decoding, is proposed and its performance is analyzed in this paper. As results, hybsrid decision decoding shows a little bit higher residual bit error rate than soft decision decoding. However, as the size of the extended hamming code increases, the difference of th enumber of comparisons increases further. In addition, hybrid decision decoding shows almost same residual bit error rate as hard decision decoding with retrassmission and shows much lower residual bit error rate than hard decision decoding without retransmission.

• 방송공학회논문지
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• 제22권1호
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• pp.42-50
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• 2017

비트의 심도 확장은 영상을 표현하는 비트 수를 확장하는 방법이다. HDR(High Dynamic Range) 디스플레이의 발전과 디스플레이의 해상도가 높아짐에 따라서, 디스플레이에서 영상을 표현하는 휘도가 증가하고 표현력도 상승한다. 이러한 디스플레이에 대응하기 위해서는 영상을 표현하는 비트수도 확장되어야 하기 때문에 비트의 심도 확장의 중요성은 높아지고 있다. 본 논문에서는, 높은 비트 심도(10bit)를 가지는 디스플레이에 기존의 영상(8bit)을 자연스럽게 표현하기 위한 비트 심도 확장 방법을 소개한다. 정량적인 결과와 정성적인 결과 및 연산량의 비교를 통해서 제안된 알고리즘이 기존의 비트 심도 확장 방법과 비교해서 우수함을 검증하였다. 제안된 방법은 기존의 최신 비트 심도 확장 방법과 비교해서, 40배 더 빠른 연산속도와 평균 1db이상 높은 성능 향상 결과를 보여준다.

• 전자공학회논문지A
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• 제29A권7호
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• pp.1-9
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• 1992

In this thesis, the trellis detection scheme is proposed to improve the error performance of the noncoherent detection in the TFM system. Trellis detection takes advantage of the trellis property of TFM-encoded signals. The trellis property is created by giving correlations among adjacent TFM-encoded signals at the transmitter. The performance of the trellis detection scheme is analyzed by means of the Bernoulli trials with the average symbol error probability, and is compared to that of the bit-by-bit detection scheme. As a result,when the SNR is below 20 dB in the Rayleigh fading and AWGN channel, the trellis detection is inferior to the bit-by-bit detections. But when SNR is above 20 dB, the trellis detection is superior to the bit-by-bit detection, and its performance enhancement is better as the SNR increases.

• IEIE Transactions on Smart Processing and Computing
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• 제3권4호
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• pp.161-166
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• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.

• 전자공학회논문지A
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• 제32A권9호
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• pp.1177-1183
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• 1995

This paper proposes a new modulation scheme of $\pi$/4-DQPSK with stepped phase for a frequency selective fading channel. In the proposed modulation scheme, the phase of transmitted signal is shifted in the mid of a symbol duration in order to reduce the effect of multipath delay spread. It reduces the irreducible error of $\pi$/4-DQPSK over a frequency selective fading channel. It is shown that $\pi$/4-DQPSK with stepped phase achieves smaller average bit error probability than regular $\pi$/4- DQPSK by simulation. The former achieves much smaller average bit error probability than the latter for small TEX>${\tau}/T_{s}$.

• 전자공학회논문지A
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• 제32A권12호
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• pp.220-228
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• 1995

An optimized 4-stage 12-bit pipelined CMOS analog-to-digital converter (ADC) architecture is proposed to obtain high linearity and high yield. The ADC based on a multiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted-capacitor (BWC) array in the front-end stage and a unit-capacitor (UC) array in the back-end stages to improve integral nonlinearity (INL) and differential nonlinearity (DNL) simultaneously whil maintaining high yield. A digital-domain nonlinear error calibration technique is applied in the first stage of the ADC to improve its accuracy to 12-bit level. The largest DNL error in the mid-point code of the ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is simulated to prove the effectiveness of the proposed ADC architecture.

• The Journal of the Acoustical Society of Korea
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• 제24권2E호
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• pp.61-66
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• 2005

Experimental work in underwater acoustic communications using passive phase conjugation has shown that the demodulation error depends on the relative drift rate between the source and receiver [Rouseff et al., IEEE J. Oceanic Eng. 26, 821-831 (2001)]. The observed effect involves the mismatch between the initial impulse response and the subsequent response after the source or receiver has changed locations. In the present work, the effect of drifting source is analyzed by numerical simulations and compared to the experimental results. The communications bit error rate is qualified as a function of drift rate, drifting direction, and source-receiver range.

• 정보보호학회논문지
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• 제27권2호
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• pp.193-199
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• 2017

본 논문에서는 정수 모듈러 N(홀수) 연산을 모듈러$(2^r-1)N$ 연산으로 변환하여 연산중 발생하는 오류를 탐지하는 방법을 제시한다. 제안하는 방법은 모듈러 직렬 곱셈기의 경우 공간 복잡도는 50% 정도, 시간 복잡도는 1% 미만 증가한다, 제안하는 방법은 r=2 인 경우 1 비트 오류는 99%, 2 비트 오류는 50%, r=3 인 경우 1, 2 비트 오류를 99% 탐지가 가능한 효율적인 오류 탐지 방법이다.

• 대한전자공학회논문지
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• 제27권4호
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• pp.484-490
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• 1990

In speech coding scheme, because information bits have different error sensitivities over channel errors, the channel coder for combining with speech coding should be realized by the variable coding rate considering the bit importance of speech information bits. In realizing the 4 kbps channel coder for 12kbps speech, this paper have chosen the channel coding method by analyzing the hard-decision post-decoding error rate of RCPC(Rate Compatible Punctured Convolutional) codes and bit error sensitivity of 12 kbps speech. Under the coherent QPSK and Rayleigh fading channel, the performance analysis has showed that 10dB gain was obtained in speech SEGSNR by 4-level uneuqal error protection, which was compared with the caseof no channel coding at 7dB channel SNR.

• 한국정보통신학회논문지
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• 제10권1호
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• pp.104-110
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• 2006

고정도, 저주파용 데이터 변환기로 사용되어온 델타-시그마 변환기는 그 출력 단에 1 bit 혹은 multi-bit 양자화기(ADC)를 사용할 수 있다. 이 중 multi-bit 양자화기를 사용하는 경우 궤환회로에도 multi-bit DAC을 사용하여야 하며 시스템의 데이터 변환 정확도는 DAC의 비선형성에 직접적인 영향을 받는다. 이 영향을 최소화하여 델타-시그마 변환기의 변환 정확도를 높이기 위해서는 DAC에 사용되는 단위 데이터 변환소자 간의 오차가 시스템에 미치는 영향을 최소화 하여야한다. 이 과정 즉 Dynamic Element Matching을 위하여 제안된 4가지 방안(DER, CLA, ILA, DWA)을 비교 설명하였다. 그리고 각 방안을 사용하였을 때 시스템 출력의 잡음 특성을 비교 하였다. 이중 DWA(Data Weighted Averaging) 방안이 가장 우수한 출력 특성을 보였다.