• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.739-743
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• 2013

In this paper, a two-dimensional (2-D) channel code for magnetic patterned media is proposed. Patterned media records an information bit on a magnetized dot. Since the space between adjacent tracks is narrow in order to increase the storage density, inter-track interference (ITI) and inter-symbol interference (ISI) can be problems. The amplitude of a bit signal can be corrupted by the 2-D ISI. The signal of the bit surrounded by the same value can be especially destructive, i.e. when its value is the same as the values of the eight surrounding bits. The proposed modulation coding scheme improves the decoding performance of patterned media by preventing this worst case and provides a better code rate than conventional channel codes.

• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.4
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• pp.195-201
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• 2023

The degree of contribution each sensor makes towards the total information gathered by all sensors is not uniform in spatially correlated sensor fields. Considering bit allocation problem in such a spatially correlated sensor field, the number of bits to be allocated to each sensor should be proportional to the degree of contribution the sensor makes. In this paper, we deploy Shapley value, a representative solution concept in cooperative game theory, and utilize it in order to quantify the degree of contribution each sensor makes. Shapley value is a system that determines the contribution of an individual player when two or more players work in collaboration with each other. To this end, we cast the bit allocation problem into a cooperative game called bit allocation game where sensors are regarded as the players, and a payoff function is given in the criteria of mutual information. We show that the Shapley value fairly quantifies an individual sensor's contribution to the total payoff achieved by all sensors following its desirable properties. By numerical experiments, we confirm that sensor that needs more bits to cover its area has larger Shapley value in spatially correlated sensor fields.

• Current Optics and Photonics
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• v.8 no.4
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• pp.345-354
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• 2024

The bit walk-off effect caused by fiber dispersion and carrier reuse in the base station (BS) are two key problems in radio-over-fiber (ROF) systems. In this paper, a novel frequency-octupling ROF system based on the Mach-Zehnder modulator (MZM) is proposed, which can overcome the bit walk-off effect and realize carrier reuse by inserting pilot signals. Theoretical analysis and simulation verification of the system are carried out. Under the condition of a Q factor greater than 6, the optical fiber transmission distance of the upper and lower links is more than 290 km and 80 km, respectively. The influence of the main device parameters of the system on the Q factor is analyzed when they deviate from their designed values. The system designed in this paper can not only effectively overcome the bit walk-off effect, but also solve the problem of downlink performance degradation and the limitation of tunability caused by conventional carrier reuse in ROF. The system can greatly increase the transmission distance and improve the performance of the system and has an important application prospect in ROF.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.26-35
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• 1997

This paper proposes a multi-bit $\Sigma\Delta$ modulator arcitecture which eliminates signal clipping problem. To avoid signal clipping, the output values of intgrators are monitored and modified by a reference value. This oepration is recorded as a digital code to restore actual signal value. Due to the digital code, the substraction of feedback value from the multi-bit quantizer can be calculated by a digital adder and this simplifies dAC operation making the accurate DAC of conventional multi-bit $\Sigma\Delta$ modulator scheme unnecessary. These features make N-th modulator can be implemented by sharing an integrator among N stages to decrease the required chip area. As an experimental example, a 4th order .sum..DELTA. modulator with oversampling ratio of 64 was simulated to show over 130 DB SNR at rail-to-rail input sinusoidal signal.

• Journal of Korea Society of Digital Industry and Information Management
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• v.4 no.4
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• pp.9-19
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• 2008

In this paper, it is studied anti-collision algorithm based on the transmission protocol for RFID baseband system of the lSO/IEC 18000-6 Type-C regulation and designed the baseband part of RFID reader system using FPGA. To compensate this weak point of the slot random aloha algorithm which must have a long time to be dumped before deciding an appropriate slot size according to the number of surrounding tag, we suggested how to apply Bit By Bit algorithm to be able to recognize the tag when the tag is clashing. The design of the baseband part in the RFID reader system is accomplish by use of the ISE9.1i and I made an experiment on it targeting Spartan2. Construction verification is measured each block through Logic Analyzer and I can verify it has no error. I also compared and analyzed the performance between proposed algorithm and past algorithm and verified the improvement of performance.

• Progress in Superconductivity
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• v.5 no.1
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• pp.21-25
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• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.193-198
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• 2005

NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.67-72
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• 1994

In this paper we suggest a 32 bit high speed parallel multiplier which plays an important role in digital signal processing. We employ a bit-pair recoding Booth algoritham that gurantees n/2 partial product terms, which uniformly handles the signed-operand case. While partial product terms are generated, a special method is suggested to reduce time delay by employing 1's complement instead of 2's complement. Later when partial products are added, the additional 1 bit's are packed in a single partial product term and added to in the parallel counter. Then 16 partial product terms are reduced to two summands by using successive parallel counters. Final multiplication value is obtained by a BLC adder. When this multiplier is simulated under 0.8$\mu$CMOS standard cell we obtain 30ns multiplier speed.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2056-2059
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• 2003

The rate control is very important to solve the difficulties arising from bit-rate on transmission through channel and to improve video quality. It is very important to point out that the amount of output bit obtained the encoding process using rate controller brings many problems on the transmission of channels and furthermore output bitstream decoded affects directly on the visual quality of displayed subject. In this paper, the effective rate control algorithm by rate-distortion modeling using MPEG-4 encoder is proposed. The proposed rate control has applied different weighting by VOP prediction type and even in the same VOP prediction type, the predicted reference allocates more bit. Through these bit allocation the minimization of distortion can be achieved preventing propagation of quantization error The amount of saved bitstream obtained by the proposed algorithm in this thesis is allocated to I-VOP using region of interest(ROI) selective enhancement on the next GOV encoding process and this process brought the improvement of visual quality.

• The Journal of the Acoustical Society of Korea
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• v.18 no.4E
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• pp.43-50
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• 1999

A fast converging coding algorithm that adaptively selects the modes of macroblocks is introduced. For a given frame, the optimal modes are selected based on the decision curves that minimize the overall distortion at a given bit rate. The method proposed in this paper is different from the conventional ones in that it does not manipulate the quantizer to meet the target bit rate but it satisfies the target bit rate by finding optimal modes of macroblocks which result consistent visual quality. Lagrange multiplier of the unconstrained cost function is controlled to trigger decision curves to generate appropriate modes to meet bit rate and the curve is obtained by utilizing simulated annealing optimization technique. The algorithm is implemented within H.261 video codec and simulation results demonstrate superior visual quality.