• Title/Summary/Keyword: Bit

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Bit Depth Expansion using Error Distribution (에러 분포의 예측을 이용한 비트 심도 확장 기술)

  • Woo, Jihwan;Shim, Woosung
    • Journal of Broadcast Engineering
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    • v.22 no.1
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    • pp.42-50
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    • 2017
  • A Bit-depth expansion is a method to increase the number of bit. It is getting important as the needs of HDR (High Dynamic Range) display or resolution of display have been increased because the level of luminance or expressiveness of color is proportional to the number of bit in the display. In this paper, we present effective bit-depth expansion algorithm for conventional standard 8 bit-depth content to display in high bit-depth device (10 bits). Proposed method shows better result comparing with recently developed methods in quantitative (PSNR) with low complexity. The proposed method shows 1db higher in PSNR measurement with 40 times faster in computational time.

Development and Security Analysis of GIFT-64-Variant That Can Be Efficiently Implemented by Bit-Slice Technique (효율적인 비트 슬라이스 구현이 가능한 GIFT-64-variant 개발 및 안전성 분석)

  • Baek, Seungjun;Kim, Hangi;Kim, Jongsung
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.30 no.3
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    • pp.349-356
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    • 2020
  • GIFT is a PRESENT-like cryptographic algorithm proposed in CHES 2017 and used S-box that can be implemented through a bit-slice technique[1]. Since bit-permutation is used as a linear layer, it can be efficiently implemented in hardware, but bit-slice implementation in software requires a specific conversion process, which is costly. In this paper, we propose a new bit-permutation that enables efficient bit-slice implementation and GIFT-64-variant using it. GIFT-64-variant has better safety than the existing GIFT in terms of differential and linear cryptanalysis.

Bit-sliced Modular Multiplication Algorithm and Implementation (비트 확장성을 갖는 모듈러 곱셈 알고리즘 및 모듈러 곱셈기 설계)

  • 류동렬
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.10 no.3
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    • pp.3-10
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    • 2000
  • In this paper we propose a bit-sliced modular multiplication algorithm and a bit-sliced modular multiplier design meeting the increasing crypto-key size for RSA public key cryptosystem. The proposed bit-sliced modular multiplication algorithm was designed by modifying the Montgomery's algorithm. The bit-sliced modular multiplier is easy to expand to process large size operands and can be immediately applied to RSA public key cryptosystem.

Sweet spot search of multi peak beam using Genetic Algorithm (Genetic Algorithm을 이용한 멀티 피크 빔의 최적방향탐색)

  • Hwang Jong Woo;Lim Sung Jin;Eom Ki Hwan;Sato Yoichi
    • Proceedings of the IEEK Conference
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    • 2004.06a
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    • pp.301-304
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    • 2004
  • In this paper, we propose a method to find the optimal direction of the multi beam between each station on the point-to-point link by genetic algorithm. In the proposed method, maximum value in optimal direction on each station is used as a fitness function. The beam of millimeter wave generates a lot of multi-peak because of much influence of noise. About each gene, we simulated this method using 16bit, 32bit, and 32bit split algorithm. 32bit split uses 16bit gene information. Each antenna makes 32bit gene information by adding gene information of two antennas having 16bit gene. Through the proposed method, we could have gotten a good output without 32bit gene information.

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A Stack Bit-by-Bit Algorithm for RFID Multi-Tag identification (RFID 다중 태그 인식을 위한 STACK Bit-by-Bit 알고리즘)

  • Lee, Jae-Ku;Yoo, Dea-Suk;Choi, Jae-Won;Choi, Seung-Sik
    • Proceedings of the Korea Information Processing Society Conference
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    • 2007.05a
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    • pp.795-798
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    • 2007
  • RFID 리더기가 영역내의 다수의 태그를 인식하기 위해선 충돌방지 알고리즘이 필수적으로 요구된다. 본 논문은 Auto ID Class 0에서 정의한 충돌방지 알고리즘인 Bit-by-Bit 이진트리 알고리즘(BBB)의 충돌 위치를 스택에 저장하고 이를 통해 다음 질의어를 결정함으로써 성능이 크게 개선된 Stack-bit-by-bit(SBBB) 알고리즘을 제안한다. 시뮬레이션을 통한 검증결과 질의-응답 횟수, 질의어의 크기, 응답어의 크기의 모든 면에서 성능이 개선된 것을 확인할 수 있었다.

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Bit-slice Modular multiplication algorithm (비트 슬라이스 모듈러 곱셈 알고리즘)

  • 류동렬;조경록;유영갑
    • The Journal of Information Technology
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    • v.3 no.1
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    • pp.61-72
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    • 2000
  • In this paper, we propose a bit-sliced modular multiplication algorithm and a bit-sliced modular multiplier design meeting the increasing crypto-key size for RSA public key cryptosystem. The proposed bit-sliced modular multiplication algorithm was designed by modifying the Walter's algorithm. The bit-sliced modular multiplier is easy to expand to process large size operands, and can be immediately applied to RSA public key cryptosystem.

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Programming Characteristics of the Multi-bit Devices Based on SONOS Structure (SONOS 구조를 갖는 멀티 비트 소자의 프로그래밍 특성)

  • 김주연
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.9
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    • pp.771-774
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    • 2003
  • In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

HEVC 10bit Bitstream Decoding Method for Low Memory Bandwidth (낮은 메모리 대역폭을 위한 HEVC 10bit 비트스트림 복호화 방법)

  • Jang, Seungchul;Lee, Jongseok;Park, Seanae;Sim, Donggyu
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2018.06a
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    • pp.100-101
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    • 2018
  • 본 논문에서는 8bit 영상으로 복원하여 메모리 사용량을 줄이는 HEVC 10bit bitstream 의 복호화 방법을 제안한다. 제안하는 방법은 10bit HEVC 비트스트림을 양자화 과정에서 10bit 양자화 계수로 변환하고 이후에 8bit 복호화를 진행하여 메모리 사용량을 절반만 사용하는 복호화를 수행한다. 실험 결과는 제안하는 방법을 적용하였을 때, 10bit 비트스트림의 기존 복호화 방법을 원본으로 PSNR 을 비교하였다. 그 결과 Y, U, V 각각 평균 32.79dB, 39.87dB, 39.79dB 을 보인다.

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Design and Implemetation of EasyWeb that searching and sharing to Informations (정보 검색 및 공유가 가능한 EasyWeb 설계 및 구현)

  • Gang, Sang-Eun;Kim, Taek-Hwan;Kang, Min-Young;Joo, Ok-Chan;Kim, Jin-Mook
    • Proceedings of the Korea Information Processing Society Conference
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    • 2011.11a
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    • pp.1411-1413
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    • 2011
  • 기존의 인터넷 검색 편리성을 제공하는 브라우저들은 사용자의 요구에 따라 수동적으로 움직이게 된다. 또한 RSS 와 같은 고급 검색 요구 조건을 만족시키고자 하는 노력에 비하여 사용자의 요구에 따라 능동적으로 움직이기에는 어려움이 존재한다. 이에 본 연구에서는 RSS와 같은 능동적인 정보 검색 및 제공이 가능하고, 표준 HTML2.0을 따르는 효과적인 웹 브라우저인 EasyWeb을 설계 및 구현하고자 한다. 본 논문에서 제안한 EasyWeb 브라우저는 기존의 브라우저들과 달리 표준 규격에 따라 구성하도록 HTML과 XML parsing이 가능하다. 또한 사용자의 요구에 능동적으로 정보를 수집하여 제공할 수 있다. 본 논문에서 제안한 EasyWeb의 구현 결과를 살펴보면 향후 웹 브라우저의 나아갈 방향을 모색할 수 있을 것으로 생각된다.

Reduced-bit transform based block matching algorithm via SAD (영상의 저 비트 변환을 이용한 SAD 블록 정합 알고리즘)

  • Kim, Sang-Chul;Park, Soon-Yong;Chien, Sung-Il
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.1
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    • pp.107-115
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    • 2014
  • The reduced-bit transform based bit-plane matching algorithm (BPM) can obtain the block matching result through its simple calculation and hardware design compared to the conventional block matching algorithms (BMAs), but the block matching accuracy of BPMs is somewhat low. In this paper, reduced-bit transform based sum of the absolute difference (R-SAD) is proposed to improve the block matching accuracy in comparison with the conventional BPMs and it is shown that the matching process can be obtained using the logical operations. Firstly, this method transforms the current and the reference images into their respective 2-bit images and then a truth table is obtained from the relation between input and output 2-bit images. Next, a truth table is simplified by Karnaugh map and the absolute difference is calculated by using simple logical operations. Finally, the simulation results show that the proposed R-SAD can obtain higher accuracy in block matching results compared to the conventional BPMs through the PSNR analysis in the motion compensation experiments.