• Journal of the Korean Chemical Society
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• v.14 no.2
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• pp.193-199
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• 1970

Further validity of the significant structure theory has been tested by calculating the viscosities of binary mixtures-three pairs of $C_6H_6(1)+C_6H_{12}\;(2),\;CCI_4\;(1)+C_6H_6{2}and\l;CCI_4(1)+C_6H_{12}(2)$-and also by calculating the viscosities of n-$C_5H_{12}\;and\;n-C_6H_{14}$ in the pressure range of 1 bar to 4000 bars. The results are quite satisfactory for both cases and provide another evidence for the validity of the significan structure theory.

• Journal of the Korean Chemical Society
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• v.10 no.3
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• pp.136-142
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• 1966

The Transient State Theory of Significant Liquid Structure has been successfully extended to binary mixture, benzene-cyclohexane system, which gives positive deviation from Raoult's law. The partition function has been derived, and from it various thermodynamic properties, such as total and partial vapor pressures, molar volumes, and excess entropies have been calculated at the temperatures $303.15^{\circ},\;\313.15^{\circ},\;and\;343.15^{\circ}K$. The calculated values agree satisfactorily with the experimental data.

• ETRI Journal
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• v.30 no.4
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• pp.495-505
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• 2008

This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, $1+x^2+x^5$, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.06a
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• pp.175-177
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• 2018

This paper proposes an algorithm to speed up block structure partition of quad tree plus binary tree (QTBT) in Joint Exploration Test Model (JEM) encoder. The proposed fast encoding of QTBT block partition employs three spatially neighbor coded blocks, such as left, top-left, and top of current block, to early terminate QTBT block structure pruning. The propose algorithm is organized based on statistical similarity of those spatially neighboring blocks, such as block depths and coded block types, which are coded with overlapped block motion compensation (OBMC) and adaptive multi transform (AMT). The experimental results demonstrate about 30% encoding time reduction with 1.3% BD-rate loss on average compared to the anchor JEM-7.1 software under random access configuration.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.774-780
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• 2017

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.724-727
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.1976-1979
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.185-191
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• 1999

Mathematical morphology based on set theory has been applied to various areas in image processing. Pitas proposed a object recognition algorithm using Morphological Shape Decomposition(MSD), and a new representation scheme called Morphological Shape Representation(MSR). The Pitas's algorithm is a simple and adequate approach to recognize objects that are rotated 45 degree-units with respect to the model object. However, this recognition scheme fails in case of random rotation. This disadvantage may be compensated by defining small angle increments. However, this solution may greatly increase computational complexity because the smaller the step makes more number of rotations to be necessary. In this paper, we propose a new method for object recognition based on MSD. The first step of our method decomposes a binary shape into a union of simple binary shapes, and then a new tree structure is constructed which ran represent the relations of binary shapes in an object. finally, we obtain the feature informations invariant to the rotation, translation, and scaling from the tree and calculate matching scores using efficient matching measure. Because our method does not need to rotate the object to be tested, it could be more efficient than Pitas's one. MSR has an intricate structure so that it might be difficult to calculate matching scores even for a little complex object. But our tree has simpler structure than MSR, and easier to calculated the matchng score. We experimented 20 test images scaled, rotated, and translated versions of five kinds of automobile images. The simulation result using octagonal structure elements shows 95% correct recognition rate. The experimental results using approximated circular structure elements are examined. Also, the effect of noise on MSR scheme is considered.

• The Bulletin of The Korean Astronomical Society
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• v.33 no.2
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• pp.64.1-64.1
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• 2008

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.441-449
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• 2000

Binary volume data has its widespread use in the application of color volume rendering and surgical simulation system where gray-scale volume is inappropriate. For the efficient representation of binary volume, this paper proposes a new data structure - the Slice-based Binary Shell (SBS) - along with its rendering algorithm. Since SBS stores the minimal set of surface voxels in slice order and supports the direct computation of voxel coordinates, it shows high efficiency for rendering multiple objects. The rendering algorithm of SBS running on a PC with no specialized hardware renders more than one hundred binary objects in a second.