• Corrosion Science and Technology
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• v.23 no.2
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• pp.93-103
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• 2024

In the present work, a phase-field model for dendritic solidification is applied to hot-dip ZnAlMg coatings to elucidate the morphology of zinc dendrites and the solute segregation leading to the formation of eutectics. These aspects define the microstructure that conditions the corrosion resistance and the mechanical behaviour of the coating. Along with modelling phase transformation and solute diffusion, the implemented model is partially coupled with the tracking of crystal orientation in solid grains, thus allowing the effects of surface tension anisotropy to be considered in multi-dendrite simulations. For this purpose, the composition of a hot-dip ZnAlMg coating is assimilated to a dilute pseudo-binary system. 1D and 2D simulations of isothermal solidification are performed in a finite element solver by introducing nuclei as initial conditions. The results are qualitatively consistent with existing analytical solutions for growth velocity and concentration profiles, but the spatial domain of the simulations is limited by the required mesh refinement.

• Journal of IKEEE
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• v.23 no.1
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• pp.58-67
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• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.235-242
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• 2005

In this paper, we propose a new division circuit for $GF(2^m)$ applications. The proposed division circuit is based on a modified the binary GCD algorithm and produce division results at a rate of one per 2m-1 clock cycles. Analysis shows that the proposed circuit gives $47\%$ and $20\%$ improvements in terms of speed and hardware respectively. In addition, since the proposed circuit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Thus, the proposed divider. is well suited to low-area $GF(2^m)$ applications.

• Bulletin of the Korean Mathematical Society
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• v.32 no.2
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• pp.337-342
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• 1995

A semiring is a binary system $(S, +, \times)$ such that (S, +) is an Abelian monoid (identity 0), (S,x) is a monoid (identity 1), $\times$ distributes over +, 0 $\times s s \times 0 = 0$ for all s in S, and $1 \neq 0$. Usually S denotes the system and $\times$ is denoted by juxtaposition. If $(S,\times)$ is Abelian, then S is commutative. Thus all rings are semirings. Some examples of semirings which occur in combinatorics are Boolean algebra of subsets of a finite set (with addition being union and multiplication being intersection) and the nonnegative integers (with usual arithmetic). The concepts of matrix theory are defined over a semiring as over a field. Recently a number of authors have studied various problems of semiring matrix theory. In particular, Minc [4] has written an encyclopedic work on nonnegative matrices.

• East Asian mathematical journal
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• v.29 no.5
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• pp.529-536
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• 2013

In this paper, we find the values and the number of occurrences of each value of the cross-correlation function $C_d({\tau})$ when $d=\frac{2^{k-1}}{2^s-1}(2^{k(i+1)}-2^{ki}+2^{s+1}-2^k-1)$, where n = 2k, s is an integer such that 2s divides k, and i is odd.

• International Journal of Naval Architecture and Ocean Engineering
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• v.7 no.1
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• pp.87-99
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• 2015

In recent years, the development of autonomous surface vehicles has been a field of increasing research interest. There are two major areas in this field: control theory and path planning. This study focuses on path planning, and two objectives are discussed: path planning for Unmanned Surface Vehicles (USVs) and implementation of path planning in a real map. In this paper, satellite thermal images are converted into binary images which are used as the maps for the Finite Angle $A^*$ algorithm ($FAA^*$), an advanced $A^*$ algorithm that is used to determine safer and suboptimal paths for USVs. To plan a collision-free path, the algorithm proposed in this article considers the dimensions of surface vehicles. Furthermore, the turning ability of a surface vehicle is also considered, and a constraint condition is introduced to improve the quality of the path planning algorithm, which makes the traveled path smoother. This study also shows a path planning experiment performed on a real satellite thermal image, and the path planning results can be used by an USV.

• ETRI Journal
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• v.31 no.2
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• pp.129-139
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• 2009

This paper provides an efficient algorithm for computing the ${\eta}_T$ pairing on supersingular elliptic curves over fields of characteristic two. In the proposed algorithm, we deploy a modified multiplication in $F_{2^{4n}}$ using the Vandermonde matrix. For F, G ${\in}$ $F_{2^{4n}}$ the proposed multiplication method computes ${\beta}{\cdot}F{\cdot}G$ instead of $F{\cdot}G$ with some ${\beta}$ ${\in}$ $F^*_{2n}$ because ${\beta}$ is eliminated by the final exponentiation of the ${\eta}_T$ pairing computation. The proposed multiplication method asymptotically requires only 7 multiplications in $F_{2^n}$ as n ${\rightarrow}$ ${\infty}$, while the cost of the previously fastest Karatsuba method is 9 multiplications in $F_{2^n}$. Consequently, the cost of the ${\eta}_T$ pairing computation is reduced by 14.3%.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• Journal of Information Processing Systems
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• v.15 no.2
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7A
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• pp.547-556
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• 2003

This paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for low-area elliptic curve cryptographic processor. The proposed arithmetic unit, which is linear feed back shift register (LFSR) architecture, is designed by using hardware sharing between the binary GCD algorithm and the most significant bit (MSB)-first multiplication scheme, and it can perform both division and multiplication in GF(2$^{m}$ ). In other word, the proposed architecture produce division results at a rate of one per 2m-1 clock cycles in division mode and multiplication results at a rate of one per m clock cycles in multiplication mode. Analysis shows that the computational delay time of the proposed architecture, for division, is less than previously proposed dividers with reduced transistor counts. In addition, since the proposed arithmetic unit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Therefore, the proposed novel architecture can be used for both division and multiplication circuit of elliptic curve cryptographic processor. Specially, it is well suited to low-area applications such as smart cards and hand held devices.