• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.8
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• pp.1911-1932
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• 2013

Orthogonal frequency-division multiplexing (OFDM) has become a popular modulation scheme for wireless protocols because of its spectral efficiency and robustness against multipath interference. Although the components of various OFDM protocols are functionally similar, they remain distinct because of the characteristics of the environment. Recently, graphics processing units (GPUs) have been used to accelerate the signal processing of the physical layer (PHY) because of their great computational power, high development efficiency, and flexibility. In this paper, we describe the implementation of parameterized baseband modules using GPUs for two different OFDM protocols, namely, 802.11a and 802.16. First, we introduce various modules in the modulator/demodulator parts of the transmitter and receiver and analyze the computational complexity of each module. We then describe the integration of the GPU-based baseband modules of the two protocols using the parameterized method. GPU-based implementations are addressed to explain how to accelerate the baseband processing to archive real-time throughput. Finally, the performance results of each signal processing module are evaluated and analyzed. The experiments show that the GPU-based 802.11a and 802.16 PHY meet the real-time requirement and demonstrate good bit error ratio (BER) performance. The performance comparison indicates that our GPU-based implemented modules have better flexibility and throughput to the current ones.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.940-948
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• 2008

This paper presents a low-power, low-complexity design and implementation results of a high speed multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor is composed of the physical layer convergence procedure (PLCP) processor and physical medium dependent (PMD) processor, which have been optimized to have low-power and reduced-complexity architecture. It was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. As a result, the proposed TX-PLCP processor reduced the power consumption by as much as 81% over the bit-level operation architecture. Also, the proposed MIMO symbol detector reduced the hardware complexity by 18% over the conventional SQRD-based architecture with division circuits and square root operations.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.2
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• pp.87-95
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• 2002

In this paper, we proposed a fast multi-resolution motion estimation(MRME) algorithm. This algorithm exploits the half-pixel accuracy motion estimation(HPAME) for exact motion vectors in the baseband and block classification for the reduction of bit amounts and computational loads. Generally, as the motion vector in the baseband are used as initial motion vector in the high frequency subbands, it has crucial effect on quality of the motion compensated image. For this reason, we exploit HPAME in the motion estimation for the baseband. But HPAME requires additional bit and computational loads so that we use block classification for the selective motion estimation in the high frequency subbands to compensate these problems. In result, we could reduce the bit rate and computational load at the similar image quality with conventional MRME. The superiority of the proposed algorithm was confirmed by the computer simulation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.109-114
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• 2023

In this paper, a 2-channel Image-Reject receiver using a 65-nm CMOS process is presented for Ka-band compact radars. The designed receiver consists of Low-Noise Amplifier (LNA), IQ mixer, and Analog Baseband (ABB). ABB includes a complex filter in order to suppress unwanted images, and the variable gain amplifiers (VGAs) in RF block and ABB have gain tuning range from 4.5-56 dB for wide dynamic range. The gain of the receiver is controlled by on-chip SPI controllers. The receiver has noise figure of <15 dB, OP1dB of >4 dBm, image rejection ratio of >30 dB, and channel isolation of >45 dB at the voltage gain of 36 dB, in the Ka-band target frequency. The receiver consumes 420 mA at 1.2 V supply with die area of 4000×1600 ㎛.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.678-684
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• 2013

This paper describes a low-power baseband circuit for SAW-less LTE-Advanced transmitters. The proposed transmitter baseband circuit consists of a 2nd-order Tow-Thomas type active RC-LPF and a 1st-order passive RC LPF. It can provide a 7 multi-channel cut-off frequencies and wide gain control range of -41 dB ~ 0 dB with a 1-dB step. The proposed 2nd-order active RC-LPF adopts an op-amp in which three other sub-op amps are in parallel connected to reduce DC current for different cutoff frequency. In addition, each sub-op amp adopts both Miller and feed-forward phase compensation method to achieve an UGBW of more than 1-GHz with a small DC power consumption. The proposed baseband circuit is implemented in 65-nm CMOS technology, consuming DC power from 6.3 mW to 24.1 mW from a 1.2V supply voltage for each different cut-off frequency.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1982.10a
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• pp.47-50
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• 1982

A baseband data transimission system is implemented on a microcomputer for performance study on some NRS line codes. These codes are compared in terms of eye width, BER, and power spectrum.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.129-132
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• 2000

This paper describes how to Implement dual band GSM hand set varying single band GSM phone. The idea can be extended to Triple mode design. Multiband design is important for global roamming and Baseband setup planning. Here H/W and SW issues are briefly described

• Proceedings of the Acoustical Society of Korea Conference
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• 1987.11a
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• pp.93-97
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• 1987

In this paper a SAW based AWZPSK modulator using the classical truncated cosine series functoins as a baseband pulse is described. A SAW AWQPSK modulator has been designed and fabricated on YZ-LINBO3 substrates. Measured responses meet the theoretical values with tolerable amounts of deviation. This SAW-based device shows good performance as a simple AWQPSK modulator.

• Bulletin of the Korean Space Science Society
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• 2007.10a
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• pp.61-61
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• 2007

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.107-112
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• 2012

In this contribution, we designed a general purpose input/output (GPIO) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. General purpose I/O should be used as multi-functional and versatile interrupt sources. We considered the edge-sensitive mode as well as the level-sensitive mode for acquiring the interrupt sources. Also, we provided an option to select the operation polarity for flexible application to the embedded systems. The designed GPIO module was automatically synthesized, placed, and routed. The proposed GPIO was implemented through the Altera FPGA and well operated at 25MHz clock frequency.