• Title/Summary/Keyword: Bare die

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The Study on the Embedded Active Device for Ka-Band using the Component Embedding Process (부품 내장 공정을 이용한 5G용 내장형 능동소자에 관한 연구)

  • Jung, Jae-Woong;Park, Se-Hoon;Ryu, Jong-In
    • Journal of the Microelectronics and Packaging Society
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    • v.28 no.3
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    • pp.1-7
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    • 2021
  • In this paper, by embedding a bare-die chip-type drive amplifier into the PCB composed of ABF and FR-4, it implements an embedded active device that can be applied in 28 GHz band modules. The ABF has a dielectric constant of 3.2 and a dielectric loss of 0.016. The FR-4 where the drive amplifier is embedded has a dielectric constant of 3.5 and a dielectric loss of 0.02. The proposed embedded module is processed into two structures, and S-parameter properties are confirmed with measurements. The two process structures are an embedding structure of face-up and an embedding structure of face-down. The fabricated module is measured on a designed test board using Taconic's TLY-5A(dielectric constant : 2.17, dielectric loss : 0.0002). The PCB which embedded into the face-down expected better gain performance due to shorter interconnection-line from the RF pad of the Bear-die chip to the pattern of formed layer. But it is verified that the ground at the bottom of the bear-die chip is grounded Through via, resulting in an oscillation. On the other hand, the face-up structure has a stable gain characteristic of more than 10 dB from 25 GHz to 30 GHz, with a gain of 12.32 dB at the center frequency of 28 GHz. The output characteristics of module embedded into the face-up structure are measured using signal generator and spectrum analyzer. When the input power (Pin) of the signal generator was applied from -10 dBm to 20 dBm, the gain compression point (P1dB) of the embedded module was 20.38 dB. Ultimately, the bare-die chip used in this paper was verified through measurement that the oscillation is improved according to the grounding methods when embedding in a PCB. Thus, the module embedded into the face-up structure will be able to be properly used for communication modules in millimeter wave bands.

Measurement of Friction Coefficient in Stretching of Coated Steel Sheets (각종 도금강판의 신장성형시 마찰계수측정)

  • Kwon, Jae-Wook;Kim, In-Soo;Lee, Dong-Nyung
    • Transactions of Materials Processing
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    • v.1 no.1
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    • pp.75-86
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    • 1992
  • Coated sheet steels have been increasingly used in automotive industry for improving corrosion resistance. One of the arised concerns is frictional behavior of coated sheet steel in stamping process. But analyses of the frictional behavior are complex and difficult. A tensile strip test has been developed for evaluating friction under the condition which simulate the stretching of sheet. Tests are conducted under different die radius and lubrication conditions. Electro-galvanized steel sheets show a lower coefficient of friction than bare steel sheets whose coated layers have been chemically removed. The coefficients of friction are independent of die radius.

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Manufacture of Dismantling Apparatus for Waste CPU Chip and Performance Evaluation (폐 CPU 칩의 해체장치 제작 및 성능 평가)

  • Joe, Aram;Park, Seungsoo;Kim, Boram;Park, Jaikoo
    • Resources Recycling
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    • v.25 no.6
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    • pp.3-12
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    • 2016
  • In this study, Au distribution in F-PGA chip and W-BGA chip were examined to recover Au effectively from CPU chips. The result showed that 80.8% and 89.8% of Au exist in terminal of F-PGA chip and bare die of W-BGA chip, respectively. Based on the fact that Au exists in specific parts of the chips, an CPU chip dismantling apparatus was developed. The experimental variables were roller rotating speed, heat temperature of IR heater and heating time. Terminals of F-PGA chips were completely recovered under the temperature of $300^{\circ}C$ and the residence time of 90 s. Bare dies of W-BGA chips were completely recovered as well under the temperature of $300^{\circ}C$, the roller rotating rate of 90 rpm and the residence time of 90 s.

Coating Properties of a TPD Organic Hole-transporting Layer Deposited using a Continuous slot-die Coating Method (연속 slot-die 코팅법을 이용한 TPD 유기 정공수송층의 코팅 특성 분석)

  • Chung, Kook Chae;Kim, Young Kuk;Choi, Chul Jin
    • Korean Journal of Metals and Materials
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    • v.48 no.4
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    • pp.363-368
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    • 2010
  • N,N'-diphenyl-N,N'-bis(3-methylphenyl)1-1' biphenyl-4,4'-diamine (TPD) hole-transporting layers were deposited using a continuous slot-die coating method on ITO/PET flexible substrates. It is crucial that the substrates have a very smooth surface with a RMS roughness of less than 2 nm for the deposition of semiconductor nanocrystals or Quantum Dots. The parameters of the slot-die coating, including the solution concentration of the TPD, the gap between the slot-die and the substrates, and the coating speed were controlled in these experiments. To obtain full coverage of the TPD films on the ITO/PET substrates (40 mm wide and several meters long), the injection rates of the TPD solution were increased proportional to the coating speed of the flexible substrates. Additionally, the injection rates must be increased as the gap distance changes from 400 to 600 ${\mu}m$ at the same coating speed. A RMS surface roughness of less than 2 nm was obtained, in contrast to bare ITO/PET substrates, at 13 nm, as the coating speed and gap distance increased.

Development of the Ka-band 20watt SSPA (Solid State Power Amplifier) Using a Spatial Combiner (공간결합기를 이용한 Ka대역 20W급 SSPA 개발)

  • Choi, Young-Rak;Lee, Jong-Woo;Lee, Su-Hyun;An, Se-Hwan;Lee, Man-Hee;Kim, Hong-Rak
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.19 no.1
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    • pp.231-238
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    • 2019
  • In this paper, we have studied how to improve the amplifiers efficiency by minimizing the combining loss when several unit power amplifiers are combined to obtain high output power. Specifically, we have developed Ka-band Spatial Combining Amplifier. The fabricated Spatial Combining Amplifier is a Ka-band 20W class SSPA, which uses a 5W class unit amplifier module 8EA designed using a GaN bare die. We also combined The unit amplifier module using 8-way spatial divider and combiner with a hybrid radial structure. The output combining loss of the fabricated spatial coupler is about 0.334dB, which is about 92.6% efficiency. In this paper, we developed a Spatial Combining Amplifier with a maximum saturation output of 10W and a power addition efficiency of over 15%. As a result, we achieved the maximum saturation output of 30W and the power addition efficiency of 19%.

Contact Pressure Effect on Frictional Behavior of Sheet Steel for Automotive Stamping (자동차용 강판의 표면 마찰 특성에 대한 접촉 압력의 영향)

  • Han, S.S.
    • Transactions of Materials Processing
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    • v.20 no.2
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    • pp.99-103
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    • 2011
  • Many parameters influence the frictional behavior of steel sheet during stamping. The contact pressure between a die and a sheet during stamping is one of them. Thus, this parameter is investigated for high strength steel (HSS) sheets, which are widely used for auto body panels due to their potential for weight reduction. Since HSS extend the limits of contact pressure for mild steel, the effect of this parameter on friction cannot be ignored. To investigate the influence of contact pressure on the frictional behavior of steel sheets, a flat type of friction test was conducted on three different steel sheets under various contact pressures. For bare steel sheets, the curve representing the relationship between contact pressure and friction coefficient exhibits a U shape. Coated steel sheets show a similar tendency except at low contact pressure. For these materials, when the contact pressure is very low, the friction coefficient slightly increases with pressure before it starts to decrease. The test results show that the effect of contact pressure on frictional behavior of steel sheet is not negligible even for contact pressures that are lower than the strength of HSS sheet.

COG 플립칩 본딩 공정조건에 따른 Au-ITO 접합부 특성

  • Choe, Won-Jeong;Min, Gyeong-Eun;Han, Min-Gyu;Kim, Mok-Sun;Kim, Jun-Gi
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2011.05a
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    • pp.64.1-64.1
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    • 2011
  • LCD 디스플레이 등에 사용되는 글래스 패널 위에 bare si die를 직접 실장하는 COG 플립칩 패키지의 경우 Au 범프와 ITO 패드 간의 전기적 접속 및 접합부 신뢰성 확보를 위해 접속소재로서 ACF (anisotropic conductive film)가 사용되고 있다. 그러나 ACF는 고가이고 접속피치 미세화에 따라 브릿지 형상에 의한 쇼트 등의 문제가 발행할 수 있어 NCP (non-conductive paste)의 상용화가 요구되고 있다. 본 연구에서는 NCP를 적용한 COG 패키지에 있어서 온도, 압력 등의 열압착 본딩 조건과 NCP 물성이 Au-ITO 접합부의 전기적 및 기계적 특성에 미치는 영향을 조사하였다. NCP는 에폭시 레진과 경화제, 촉매제를 사용하여 다양하게 포뮬레이션을 하였고 DSC (Differential Scanning Calorimeter), TGA (Thermogravimetric Analysis), DEA (Dielectric Analysis) 등의 열분석장비를 이용하여 NCP의 물성과 경화 거동을 확인하였다. 테스트 베드는 면적 $5.2{\times}7.2\;mm^2$, 두께 650 ${\mu}m$, 접속피치 200 ${\mu}m$의 Au범프가 형성된 플립칩 실리콘 다이와 접속패드가 ITO로 finish된 글래스 기판을 사용하였다. 글래스 기판과 실리콘 칩은 본딩 전 PVA Tepla사의 Microwave 플라즈마 장비로 Ar, $O_2$ 플라즈마 처리를 하였으며, Panasonic FCB-3 플립칩 본더를 사용하여 본딩하였다. 본딩 후 접합면의 보이드를 평가하고 die 전단강도로 접합강도를 측정하였다.

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A study on real time inspection of OLED protective film using edge detecting algorithm (Edge Detecting Algorithm을 이용한 OLED 보호 필름의 Real Time Inspection에 대한 연구)

  • Han, Joo-Seok;Han, Bong-Seok;Han, Yu-Jin;Choi, Doo-Sun;Kim, Tae-Min;Ko, Kang-Ho;Park, Jung-Rae;Lim, Dong-Wook
    • Design & Manufacturing
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    • v.14 no.2
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    • pp.14-20
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    • 2020
  • In OLED panel production process, it is necessary to cut a part of protective film as a preprocess for lighting inspection. The current method is to recognize only the fiducial mark of the cut-out panel. Bare Glass Cutting does not compensate for machining cumulative tolerances. Even though process defects still occur, it is necessary to develop technology to solve this problem because only the Align Mark of the panel that has already been cut is used as the reference point for alignment. There is a lot of defective lighting during panel lighting test because the correct protective film is not cut on the panel power and signal application pad position. In laser cutting process to remove the polarizing film / protective film / TSP film of OLED panel, laser processing is not performed immediately after the panel alignment based on the alignment mark only. Therefore, in this paper, we performed real time inspection which minimizes the mechanism tolerance by correcting the laser cutting path of the protective film in real time using Machine Vision. We have studied calibration algorithm of Vision Software coordinate system and real image coordinate system to minimize inspection resolution and position detection error and edge detection algorithm to accurately measure edge of panel.

Impact of Copper Densities of Substrate Layers on the Warpage of IC Packages

  • Gu, SeonMo;Ahn, Billy;Chae, MyoungSu;Chow, Seng Guan;Kim, Gwang;Ouyang, Eric
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.4
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    • pp.59-63
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    • 2013
  • In this paper, the impact of the copper densities of substrate layers on IC package warpage is studied experimentally and numerically. The substrate strips used in this study contained two metal layers, with the metal densities and patterns of these two layers varied to determine their impacts. Eight legs of substrate strips were prepared. Leg 1 to leg 5 were prepared with a HD (high density) type of strip and leg 6 to leg 8 were prepared with UHD (ultra high density) type of strip. The top copper metal layer was designed to feature meshed patterns and the bottom copper layer was designed to feature circular patterns. In order to consider the process factors, the warpage of the substrate bottom was measured step by step with the following manufacturing process: (a) bare substrate, (b) die attach, (c) applying mold compound (d) and post reflow. Furthermore, after the post reflow step, the substrate strips were diced to obtain unit packages and the warpage of the unit packages was measured to check the warpage trends and differences. The experimental results showed that the warpage trend is related to the copper densities. In addition to the experiments, a Finite Element Modeling (FEM) was used to simulate the warpage. The nonlinear material properties of mold compound, die attach, solder mask, and substrate core were included in the simulation. Through experiment and simulation, some observations were concluded.

Power Semiconductor SMD Package Embedded in Multilayered Ceramic for Low Switching Loss

  • Jung, Dong Yun;Jang, Hyun Gyu;Kim, Minki;Jun, Chi-Hoon;Park, Junbo;Lee, Hyun-Soo;Park, Jong Moon;Ko, Sang Choon
    • ETRI Journal
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    • v.39 no.6
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    • pp.866-873
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    • 2017
  • We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.