• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.131-135
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• 1989

Hot electron simulation of silicon using Monte Carlo method was carried out to investigate impact ionization characteristics near the drain of MOSFET's at 77 and 300K. We successfully characterized drift velocity and impact ionization at 77 and 300K employing a simplified energy band structure and phonon scattering mechanisms. Woods' soft energy threshold model was introduced to the Monte Carlo simulation of impact ionization, and good agreement with reported experimental results was resulted by employing threshold energy of 1.7 eV. It is suggested that the choice of the critical angle between specular reflection and diffusive scattering of surface roughness scattering may be important in determining the impact ionization charateristics of Monte Carlo simulation near the drain of MOSFET's.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.5
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• pp.1592-1596
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• 2010

According to the increase of the channel length with fixed width/length, characteristic curves of drain current as a function of gate bias voltage of indium gallium zinc oxide (IGZO) thin-film transistors moved to a positive direction of gate voltage, and field-effect mobility decreased. In case of fixed length and width of channel, field-effect mobility was lower and subthreshold slope was larger when drain bias voltage was higher. Due to large work function of IGZO, band bending at the junction region between IGZO channel and source/drain electrodes was expected to be in opposite direction to that between silicon and metal electrodes; this could explain the above results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.6
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• pp.646-652
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• 2014

This paper presents a design and fabrication of Ku-band power amplifier using Gallium Nitride High Electron Mobility Transistor (GaN HEMT) die. In order to fabricate the low-cost Ku-band power amplifier, a Printed Circuit Board(PCB) was used for input/output matching circuits instead of manufacturing process to use an expensive substrate. The measured output power is 42.6 dBm, the drain efficiency is 37.7 % and the linear gain is 7.9 dB under pulse operation at the frequency of 14.8 GHz. Under the continuous wave(CW) test, the output power is 39.8 dBm, the drain efficiency is 24.1 % and the linear gain is 7.2 dB.

• Journal of Advanced Navigation Technology
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• v.13 no.3
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• pp.358-364
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• 2009

This paper shows some variable bias techniques which can improve the power added efficiency(PAE) for the designed power amplifier. Some simulations have been done to get the effect of the bias change, and variable bias is adopted to get the higher efficiency for dual mode amplifier which generates two different output power levels. With drain bias change and a fixed gate bias, the amplifier shows PAE improvement compared to the fixed bias amplifier. In addition, this paper analyzed nonlinear distortion of the power amplifier and has used the digital predistortion which can result in 10dB ACPR improvement for the dual band amplifier.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.5
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• pp.71-78
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• 2011

In this paper, we describe the design and implementation of a high efficiency and broad-band Class-J mode power amplifier using gallium nitride(GaN) high-electron mobility transistor(HEMT). The matching circuit of proposed class-J mode power amplifier for 2nd harmonic impedance designed to provide pure reactance alone. The measurement results show that output power of $40{\pm}1$ dBm, power-added efficiency of 50%, and drain efficiency of 60% for a continuous wave signal at 1.4 to 2.6 GHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.11
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• pp.89-94
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• 2011

In this paper, we developed the W-band MMIC low noise amplifier for the millimeter-wave seeker using the tuner system. The MHEMT devices for MMIC LNA exhibited DC characteristics with a drain current density of 692mA/mm, an extrinsic transconductance of 726mS/mm. The current gain cutoff frequency(fT) and maximum oscillation frequency($f_{max}$) were 195GHz and 305GHz, respectively. The fabricated W-band low noise amplifier represented S21 gain of 7.42dB at 94 GHz and noise figure of 2.8dB at 94.2 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.506-510
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• 2016

A triple-band (TB) oscillator was implemented in the TSMC $0.18{\mu}m$ 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt $4^{th}$ order LC resonators to form a $6^{th}$ order resonator with three resonant frequencies. The oscillator uses the varactors for band switching and frequency tuning. The core current and power consumption of the high (middle, low)- band core oscillator are 3.59(3.42, 3.4) mA and 2.4(2.29, 2.28) mW, respectively at the dc drain-source bias of 0.67V. The oscillator can generate differential signals in the frequency range of 8.04-8.68 GHz, 5.82-6.15 GHz, and 3.68-4.08 GHz. The die area of the triple-band oscillator is $0.835{\times}1.103mm^2$.

• Journal of electromagnetic engineering and science
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• v.10 no.1
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• pp.6-12
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• 2010

In this paper, highly efficient class-F power amplifiers(PAs) with harmonic-controlling transmission lines(TLs) were built for cellular and WLAN applications at 840 MHz and 2.4 GHz each. Also, based on these single-band PAs, a dualband class-F PA was designed after a careful investigation into the harmonics of the two frequencies. The harmonic-controlling TL was designed for the class-F operation at dualband by switching the length of the shunt $\lambda$/4 TL part, while the series $\lambda$/4 TL is optimized for both frequencies. To verify the performance, two class-F PAs optimized at each frequency and a dualband class-F PA at the corresponding frequencies were built with the secondand the third-harmonic control circuits at each frequencies. As a result, the PA#1 at 840 MHz has a peak drain efficiency of 81.2 % with an output power of 24.4 dBm, while the PA#2 at 2.35 GHz shows a drain efficiency of 94.5 % with an output of 22.8 dBm. Finally, the dualband class-F PA#3 showed 60.5 % and 50.9 % drain efficiencies at 840 MHz and 2.4 GHz, with powers of 23.8 dBm and 19.62 dBm, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.185-190
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• 2016

A 70-${\AA}$ nanowire field-effect transistor (FET) for sub-10-nm CMOS technology is designed and simulated in order to investigate the impact of an oxide trap on random telegraph noise (RTN) in the device. It is observed that the drain current fluctuation (${\Delta}I_D/I_D$) increases up to a maximum of 78 % due to the single electron trapping. In addition, the effect of various trap positions on the RTN in the nanowire FET is thoroughly analyzed at various drain and gate voltages. As the drain voltage increases, the peak point for the ${\Delta}I_D/I_D$ shifts toward the source side. The distortion in the electron carrier density and the conduction band energy when the trap is filled with an electron at various positions in the device supports these results.