• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.183-188
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• 2002

With the contact pad consisted of $0.5{\mu}{\textrm}{m}$ $Au/5{\mu}{\textrm}{m}$ Ni/Cu layers on a conventional ball grid array(BGA) substrate, metallurgical reaction properties between the pad and In-15(wt.%)Pb-5Ag solder alloy were studied after reflow and solid aging. In as-reflow condition, thin AuIn$_2$or Ni$_{28}$In$_{72}$ intermetallic layer was formed at the solder/pad interface according to reflow time. Dissolution of the Au layer into the molten solder was remarkably limited in comparison with eutectic Sn-37Pb alloy. After solid aging of 300 hrs, thickness of In-Ni layer increased to about $2{\mu}{\textrm}{m}$ in the both as-reflow case. It was observed that In atoms diffuse through the AuIn$_2$phase to react with underlaying Ni layer. The metallurgical reaction properties between In-l5Pb-7Ag alloy and Au/Ni surface finish were analysed to result in suppression of Au-embrittlement in the solder joints.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1619-1622
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• 2002

최근에 생산되는 디지털 VLSI칩들은 그 집적도가 계속 높아지고 있으며, 이러한 칩들을 장착한 보드의 경우도 그 복잡성이 점차 높아지고 있다. 이에 따라 칩 및 보드에 대한 철저한 테스트 과정이 요구된다. 지금까지 보드 테스트 방법으로 널리 쓰였던 ICT(In-Circuit Test)는 칩의 고집적화에 따른 핀 간격의 조밀화와 SMT(Surface Mount Technology), BGA(Ball Grid Array), MCM(Multi Chip Module) 등의 새로운 패키징 방식의 등장에 따라 테스트 방법으로의 한계성을 드러내고 있다. 이에 대한 대안으로 등장한 IEEE Std 1149.1 은 ICT의 한계성을 극복할 수 있는 기술일 뿐 아니라 여러 가지 장점을 가지고 있으며 그 활용 분야도 다양하다. 본 논문에서는 IEEE Std 1149.1에 따라 설계된 보드 상에서 발생 가능한 고장들에 대한 고장 모델을 제시한다. 또한 각 고장 모델들의 양상과 진단 기법을 제시한다. 이를 통해 IEEE Std 1149.1에 따라 설계된 보드 상에서 발생한 고장들을 검출할 수 있으며, 고장의 종류 및 성격, 그리고 고장의 발생 위치 등의 정보를 얻을 수 있다. IEEE Std 1149.1에 따른 보드 설계가 보드의 신뢰성 보장에 긴요함을 인식하는 계기가 되기를 기대하며 제시된 고장 모델 및 진단 기법이 기술적으로 중요한 참고자료가 되기를 기대한다.

• Proceedings of the KWS Conference
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• 2006.05a
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• pp.30-32
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• 2006

The interfacial reaction and reliability of eutectic Sn-Pb and Pb-free eutectic Sn-Ag ball-grid-array (BGA) solders with an immersion Ag-plated Cu substrate were evaluated following isothermal aging at $150^{\circ}C$. During reflowing, the topmost Ag layer was dissolved completely into the molten solder, leaving the Cu layer exposed to the molten solder for both solder systems. A typical scallop-type Cu-Sn intermetallic compound (IMC) layer was formed at both of the solder/Cu interfaces during reflowing. The thickness of the Cu-Sn IMCs for both solders was found to increase linearly with the square root of isothermal aging time. The growth of the $Cu_3Sn$ layer for the Sn-37Pb solder was faster than that for the Sn-3.5Ag solder, In the case of the Sn-37Pb solder, the formation of the Pb-rich layer on the Cu-Sn IMC layer retarded the growth of the $Cu_6Sn_5$ IMC layer, and thereby increased the growth rate of the $Cu_3Sn$ IMC layer. In the ball shear test conducted on the Sn-37Pb/Ag-plated Cu joint after aging for 500h, fracturing occurred at the solder/$Cu_6Sn_5$ interface. The shear failure was significantly related to the interfacial adhesion strength between the Pb-rich and $Cu_6Sn_5$ IMC layers. On the other hand, all fracturing occurred in the bulk solder for the Sn-3.5Ag/Ag-plated Cu joint, which confirmed its desirable joint reliability.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.9-17
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• 2015

After its inception in 1994, the Journal of the Microelectronics and Packaging Society has continued to make significant strides in the number and quality of publications within its field. The interest in the microelectronics and packaging research has become more critical as consumer electronic products continue its increasing trend towards thinner and lighter devices that tests the boundaries of electronic devices. This study utilizes social network analysis of all published literature in the Journal for the past 22 years. Using the keywords and abstracts available within each individual article, the publications within the Journal has focused on major topics covering (1) flip chip, (2) reliability, (3) Cu, (4) IMC (intermetallic compounds), and (5) thin film. Using the social network relationship between keywords within articles, flip chip was closely associated with reliability, BGA (ball grid array), contact resistance, electromigration in many of the published research works within the Journal. From the centrality analysis, it was found that flip chip, reliability, Cu, thin film, IMC, and RF (radio frequency) to have a high degree of centrality suggesting these key areas of research have relatively high connectivity with other research topics within the Journal and is central to many of the research fields within the micro-electronics and packaging area. The cohesiveness analysis showed research clustering of five major cohesive sub-groups and was mapped to better understand the major area of research within this field. Research within the field of micro-electronics and packaging converges many disciplines of science and engineering. The continued evolution within this field requires an understanding of the rapidly changing industry environment and the consumer needs.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.59-65
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• 2011

According to the trends of electronic package to be smaller, thinner and more integrative, Flip Chip Ball Grid Array (FCBGA) become more used for mobile phone. However, the flip chip necessarily generate the heat by the electrical resistance and generated heat is increased due to reduced distribution area of the heat in accordance with the miniaturization trend of the package. Thermal issues can result in problems of devices that are sensitive to temperature and stress. Then the heat can generate problems to the system. In this paper, in order to improve the thermal issues of FCBGA, thermal characteristics of FCBGA was analyzed qualitatively by using the general heat transfer module of Comsol 3.5a and In order to solve thermal issues, flip chip with new micro structure is proposed by the simulation. and also by comparing existing model and analyzing variables such as pitch, height of the pattern and shape of the heat spreader, the improvement of heat dissipation characteristics about 18% was confirmed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.481-486
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• 2010

ENIG (electroless Ni immersion gold) is one of surface finishing which has been most widely used in fine pitch SMT (surface mount technology) and BGA (ball grid array) packaging process. The reliability for package bondability is mainly affected by interfacial reaction between solder and surface finishing. Since the behavior of IMC (intermetallic compound), or the interfacial reaction between Ni and solder, affects to some product reliabilities such as solderability and bondability, understanding behavior of IMC should be important issue. Thus, we studied the properties of ENIG with P contents (9 wt% and 13 wt%), where the P contents is one of main factors in formation of IMC layer. The effect of P content was discussed using the results obtained from FE-SEM(field-emission scanning electron microscope), EPMA(electron probe micro analyzer), EDS(energy dispersive spectroscopy) and Dual-FIB(focused ion beam). Especially, we observed needle type irregular IMC layer with decreasing Ni contents under high P contents (13 wt%). Also, we found how IMC layer affects to bondability with forming continuous Kirkendall voids and thick P-rich layer.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.27-33
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• 2008

With increasing use of portable appliances such as PDA and cellular phone, changing environment of applications requires higher solder joint reliability. The ENIG (Electroless Nickel Immersion Gold) process has been widely used for fine pitch SMT (Surface Mount Technology) and BGA (Ball Grid Array) packaged devices due to its benefits including excellent solderability, high uniformity and substantial legibility throughout the packaging process. Its brittle fracture of solder, however, has received increasingly attentions. It was Down that fracture brittleness is mainly related with black pad resulting from galvanic nickel corrosion and P-enriched layer formation between the IMC (Intermetallic Compounds) and electroless nickel layer. Theoretically, smooth electroless Ni layer was blown to have a advantages in minimizing the black pad phenomenon by uniform solution exchange during immersion gold plating. Nevertheless, how to control the surface morphology of electroless Ni layer has been hardly blown. This study investigates an effect of surface morphology of Cu underlayer on surface morphology of electroless Ni layer. To obtain various kinds of surface morphology of Cu layer, two types of Cu etching chemical and a number of Cu etching treatment were applied.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.