• 전력전자학회논문지
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• 제24권4호
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• pp.279-285
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• 2019

This study proposes an enhanced switching pattern that can improve energy transfer efficiency in an active cell-balancing circuit using a multiwinding transformer. This balancing circuit performs cell balancing by transferring energy stored in a specific cell with high energy to another cell containing low energy through a multiwinding transformer. The circuit operates in flyback and buck-boost modes in accordance with the energy transfer path. In the conventional flyback mode, the leakage inductance of the transformer and the stray inductance component of winding can transfer energy to an undesired path during the balancing operation. This case results in cell imbalance during the cell-balancing process, which reduces the energy transfer efficiency. An enhanced switching pattern that can effectively perform cell balancing by minimizing the amount of energy transferred to the nontarget cells due to the leakage inductance components in the flyback mode is proposed. Energy transfer efficiency and balancing speed can be significantly improved using the proposed switching pattern compared with that using the conventional switching pattern. The performance improvements are verified by experiments using a 1 W prototype cell-balancing circuit.

• Journal of Electrical Engineering and Technology
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• 제12권5호
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• pp.1812-1820
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• 2017

This paper analyzes a symmetric active cell balancer for a battery management system. The considered cell balancer uses a forward converter in which the circuit structure is symmetric. This cell-balancing method uses fewer switches and is simpler than the previously proposed active cell-balancing circuits. Active power switches of this cell-balancing circuit operate simultaneously with the same pulse width modulation signals. Therefore, this cell-balancing circuit requires less time to be balanced than a previous bidirectional-forward-converter-based cell balancer. This paper analyzes the operational principles and modes of this cell balancer with computer-based circuit simulation results as well as experimental results in which each unbalanced cell is equalized with this cell balancer. The maximum power transfer efficiency of the investigated cell balancer was 87.5% from the experimental results. In addition to the experimental and analytical results, this paper presents the performance of this symmetric active cell-balancing method.

• 한국정보과학회논문지:시스템및이론
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• 제26권10호
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• pp.1275-1283
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• 1999

본 논문은 CMOS 디지털 회로에서의 전력 소모의 주원인인 신호의 천이중에서 회로의 동작에 직접적인 영향을 미치지 않는 불필요한 신호의 천이인 글리치를 줄이기 위한 효율적인 알고리즘을 제시한다. 제안된 알고리즘은 회로의 지연 증가 없이 게이트 사이징과 버퍼 삽입에 의해 경로 균등(path balancing)을 이룸으로써 글리치를 감소시킨다. 경로 균등화를 위하여 먼저 게이트 사이징을 통해 글리치의 감소와 동시에, 게이트 크기의 최적화를 통해 회로 전체의 캐패시턴스까지 줄일 수 있으며, 게이트 사이징 만으로 경로 균등화가 이루어지지 않을 경우 버퍼 삽입으로 경로 균등화를 이루게 된다. 버퍼 자체에 의한 전력 소모 증가보다 글리치 감소에 의한 전력 감소가 큰 버퍼를 선택하여 삽입한다. 이때 버퍼 삽입에 의한 전력 감소는 다른 버퍼의 삽입 상태에 따라 크게 달라질 수 있어 ILP (Integer Linear Program)를 이용하여 적은 버퍼 삽입으로 전력 감소를 최대화 할 수 있는 저전력 설계 시스템을 구현하였다. 제안된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 회로의 지연 증가 없이 평균적으로 30.4%의 전력 감소를 얻을 수 있었다.Abstract This paper presents an efficient algorithm for reducing glitches caused by spurious transitions in CMOS logic circuits. The proposed algorithm reduces glitches by achieving path balancing through gate sizing and buffer insertion. The gate sizing technique reduces not only glitches but also effective capacitance in the circuit. In the proposed algorithm, the buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the additional power consumed by the inserted buffers. To determine the location of buffer insertion, ILP (Integer Linear Program) has been employed in the proposed system. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show an average of 30.4% power reduction.

• Journal of Electrical Engineering and Technology
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• 제11권3호
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• pp.629-638
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• 2016

This paper proposes a State-of-Charge (SOC) balancing control of Battery Power Modules (BPMs) for a modularized battery for Electric Vehicles (EVs) without additional balancing circuits. The BPMs are substituted with the single converter in EVs located between the battery and the inverter. The BPM is composed of a two-phase interleaved boost converter with battery modules. The discharge current of each battery module can be controlled individually by using the BPM to achieve a balanced state as well as increased utilization of the battery capacity. Also, an SOC balancing method is proposed to reduce the equalization time, which satisfies the regulation of a constant DC-link voltage and a demand of the output power. The proposed system and the SOC balancing method are verified through simulation and experiment.

• Journal of Power Electronics
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• 제12권6호
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• pp.869-877
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• 2012

This paper presents a current-balancing circuit for security lights that uses parallel-connected LEDs. The parallel connection of LEDs causes current differences between the LED strings because of characteristic deviations. These differences can reduce the lifespan of a particular point of LEDs by thermal spotting. They can also cause non-uniform luminance of the lighting device. Among the different methods for solving these problems, the method using current-balancing transformers makes it easy to compensate for current differences and it has a simple circuitry. However, while the balancing transformer has been applied to AC light sources, LEDs operate on a DC source, so the driving circuitry and the design method have to be changed and their performances must be verified. Thus in this paper, a design method of the balancing transformer network and the driving circuitry for LEDs is proposed. The proposed design method could have a smaller size than the conventional design method. The proposed circuitry is applied to three types of 100-watt LED security lights, which use different LEDs. Experimental results are presented to verify the performance of the designed driving circuits.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1881-1884
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• 2003

In some requirements of dc motor drive circuit applications are high quality output with generation of low internal conducted EMI. However the conventional dc motor drive circuits have been usually using unbalanced circuit which generates the high conducted EMI to the frame ground. This paper presents a balanced dc motor drive circuit which is effective way to reduce the common-mode noise. The circuit balancing is to make the noise pick up or occurring in both conductor lines, signal path and return path is equal in amplitude and opposite phase so that it will cancel out in the frame ground. The common-mode conducted noise reduction of this proposed dc motor drive is confirmed by experimental results.

• 조명전기설비학회논문지
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• 제29권3호
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• pp.22-29
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• 2015

The AC-LED driving system which is connected directly to alternative current source is suitable for commercialization because of it's simple structure and low cost. However, it requires additional circuits compensating for current differences between the parallel connected LED strings. In this paper, we proposed the circuit compensating for current error of the three LED strings using the Y type balancing transformer. The proposed Half-bridge AC Chopper LED driving system used the ferrite material's balancing transformer. at the same time, it is able to dimming control. The proposed system is applied to 80W AC-LED module consist of three parallel strings. Experiment results present that Power factor and THD measured with power analyzer are 0.958 and 26.473% respectively satisfied with IEC61000-3-2 harmonics standard.

• 전자공학회논문지A
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• 제32A권6호
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• pp.91-103
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• 1995

This paper presents the design of a performance-driven interconnect allocation algorithm. The algorithm is based on the idea that the clock period can be minimized by balancing the load for each of the communication paths following specific hardware modules. By performing load balancing for only the communication lines on ciritical paths, the proposed algorithm generates interconnection structures with minimum delays. This approach also shows run time efficiency. Experimental results confirm the effectiveness of the algorithm by constructing the interconnection structures such that the clock period can be minimized for several benchmark circuits available from the literature.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.235-240
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• 2007

A current-balancing segmented group-inverting transmitter is presented for multi-Gb/s single-ended parallel links. With an additional increase of 4 pins, 16-bit data is efficiently encoded to 20 pins to achieve the current balancing and eliminate the simultaneous switching noise. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with simplified logic circuits. The transmitter is designed with a $0.18{\mu}m$ CMOS technology, and simulated eye diagrams at 5Gb/s show dramatic improvements in signal integrity.

• 대한전기학회논문지
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• 제31권11호
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• pp.133-140
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• 1982

In recent years, a number of thyristor-controlled shunt compensators have been used in industrial and utility systems for phase balancing, power-factor correction and flicker reduction. This paper describes a simple and basic control scheme and circuits for shunt compensator with a fixed capacitor and thyristor-controlled reactor. Feedforward-control scheme is applied, and compensating currents are computed from the symmetrical components of the disturbed system. A 8 bit microprocessor is used for the computation of the compensating currents as well as for the measurements of the symmetric components. A 3-phase 1 KVA compensator is developed and a good reduction of the unbalance factor of the power source is achieved using it.