• Bulletin of the Korean Space Science Society
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• 2006.10a
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• pp.113-113
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• 2006

• Bulletin of the Korean Space Science Society
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• 2006.10a
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• pp.144-144
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• 2006

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.389-393
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• 1987

This paper describes the configuration of serial interconnection BUS, BitBUS, for Energy Management Systems, and it provides low cost, high performance approach in distributed data acquisition and control applications.

• Proceedings of the Korea Society of Design Studies Conference
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• 2005.10a
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• pp.82-83
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• 2005

• Journal of Korean Society of Transportation
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• v.23 no.6 s.84
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• pp.81-89
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• 2005

Real-time bus arrival information within the Bus Information System (BIS) is an invaluable resource for users that demand accurate and up-to-date bus headway information while waiting at a bus stop. The associated benefits of such a system come in two folds, that is to 1) resolve the psychological uncertainty caused by the lack of real-time bus arrival information and 2) empower the user waiting at bus stops with the ability to reliably coordinate various tasks and errands, such as a quick trip into a convenience store or restroom without fear of missing a bus pick-up. This paper discusses the appropriate methodology with which to measure the economic value of reliable bus arrival information, with particular emphasis on the psychological uncertainty in users associated with the lack of real-time headway information at bus stops. Data regarding bus transit users' willingness to pay for such a service is obtained through questionnaire surveys, and the Contingent Valuation Method is used to analyze and derive the associated economic value. Our findings indicate the monetary value associated with a real-time bus arrival information system is approximately 132.5 won/min at the 0.3 significance level.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• Journal of Korean Society of Transportation
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• v.28 no.1
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• pp.135-142
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• 2010

The convenient techniques for predicting the bus arrival time have used the data obtained from the buses belong to the same company only. Consequently, the conventional techniques have often failed to predict the bus arrival time at the downstream bus stops due to the lack of the data during congestion time period. The primary objective of this study is to overcome the weakness of the conventional techniques. The estimation model developed based on the data obtained from Bus Information System(BIS) and Bus management System(BMS). The proposed model predicts the bus arrival time at bus stops by using the data of all buses travelling same roadway section during the same time period. In the tests, the proposed model had a good accuracy of predicting the bus arrival time at the bus stops in terms of statistical measurements (e.g., root mean square error). Overall, the empirical results were very encouraging: the model maintains a prediction job during the morning and evening peak periods and delivers excellent results for the severely congested roadways that are of the most practical interest.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.18 no.2
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• pp.1-11
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• 2019

The accident of mass transit such as a bus could draw the large casualties and this induces social and economic losses. Recently, severe bus accidents caused by tiredness and inattention of bus drivers occurred and those lead to growing interest in bus accidents and the drivers' work environment. Therefore, this study analyzes the accident based on the work environment of bus drivers and route-bus categories. For the research, this study collected digital tachograph data and the bus company information for 271 domestic bus companies in 2017 and used ANOVA test and chi-square test as statistical methodologies. As a result, we figured out there are statistically significant differences in the accident according to the working environments. Especially, the present study confirmed the intracity bus with working every other day has the most frequent accidents. We expect that the results of this study be used as foundations for the improvement of working conditions to reduce route-bus accidents in the future.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.20 no.3
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• pp.20-33
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• 2021

Modern society is steadily implementing policies to encourage public transportation to cope with the growing traffic demand on limited roads. The expectation is rising for transit signal priority to ensure the speed of buses as the installation of the bus rapid transit(BRT) expands nationwide to secure the competitiveness of buses. On the other hand, the form of BRT stops without considering some aspects of bus operation may increase the number of stops on the bus, thereby reducing the effectiveness of bus signal priority applications. This study suggests the type of bus stop to increase the operation efficiency of buses by analyzing the bus signal priority effect according to the BRT station type using Hannuri-daero, Sejong. The bus signal priority is used to maximize the two-way bandwidth of passenger cars and buses. As a result of the application, the effectiveness of the bus signal priority at the stop causing the double stop of the bus was reduced drastically, and the efficiency of the bus signal priority was increased significantly after improvement. These results are expected to be used as basic data in the form of proper bus stops considering the aspects of traffic operation when designing BRT stops in new towns in the future.

• Journal of Power Electronics
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• v.9 no.3
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• pp.447-455
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• 2009

The power supply systems, which require low-voltage / high-current output has been changing from the conventional centralized power system to a distributed power system. The distributed power system consists of a bus converter and POL. The most important factor is the system stability in bus architecture design. The overlap between the output impedance of a bus converter input impedance of POL causes system instability and has been an actual problem. By increasing the bus capacitor, the system stability can be easily improved. However, due to limited space on the system board, the increasing of bus capacitors is impractical. An urgent solution of this issue is strongly desired. This paper presents the output impedance design for on-board distributed power system by means of three control schemes of a bus converter. The output impedance peak of the bus converter and the input impedance of the POL are analyzed and then conformed experimentally for stability criterion. Furthermore, the design process of each control schemes for system stability is proposed.