• 한국전자파학회논문지
• /
• 제21권6호
• /
• pp.670-680
• /
• 2010

본 논문에서는 0.13 ${\mu}m$ CMOS 공정을 사용하여, 이동단말기 탑재에 적합한 저 전력, 저 잡음 구조 개별 소자 (LNA, Mixer, VCO, frequency doubler, signal generator, down converter)들을 제안하고, 나아가 이를 하나의 칩으로 집적화 시킨 60 GHz 단일 칩 수신기 구조를 제안한다. 저전력화를 위해 current re-use 구조를 적용시킨 LNA의 경우, 11.6 mW 의 전력 소모 시, 56 GHz부터 60 GHz까지 측정된 잡음지수(NF)는 4 dB 이하이다. 저전력화를 위한 resistive mixer의 경우, Cgs의 보상 회로를 통하여 낮은 LO 신호 크기에서도 동작 가능하도록 하였다. -9.4dB의 변환 이득을 보여주며, 20 dB의 LO-RF isolation 특성을 가진다. Ka-band VCO는 4.99 mW 전력 소모 시측정된 출력 신호 크기는 27.4 GHz에서 -3 dBm이 되며, 26.89 GHz에서부터 1 MHz offset 기준으로 -113 dBc/Hz의 phase noise 특성을 보인다. 49.2 dB의 원신호 억제 효과를 보이는 Frequency Doubler는 총 전력 소모가 9.08 mW일 경우, -4 dBm의 27.1 GHz 입력 신호 인가 시 -53.2 dBm의 fundamental 신호(27.1 GHz)와 -4.45dBm의 V-band second harmonic 신호(54.2 GHz)를 얻을 수 있었으며, 이는 -0.45 dB의 변환 이득을 나타낸다. 60 GHz CMOS 수신기는 LNA, resistive mixer, VCO, frequency doubler, 그리고 drive amplifier로 구성되어 있으며, 전체 전력 소모는 21.9 mW이다. WLAN과의 호환 가능성을 위하여, IF(Intermediate Frequency) bandwidth가 5.25GHz(4.75~10 GHz)이며, RF 3 dB bandwidth는 58 GHz를 중심으로 6.2 GHz이다. 이때의 변환 손실은 -9.5 dB이며, 7 dB의 NF와 -12.5 dBm의 높은 입력 P1 dB를 보여주고 있다. 이는 60 GHz RF 회로의 저전력화, 저가격화, 그리고 소형화를 통한 WPAN용 이동단말기의 적용 가능성을 입증한다.

• ETRI Journal
• /
• 제34권6호
• /
• pp.885-891
• /
• 2012

This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제9권4호
• /
• pp.192-197
• /
• 2009

This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.

• 정보통신설비학회논문지
• /
• 제8권1호
• /
• pp.12-17
• /
• 2009

In this paper, We play it for the purpose of study about the power amplifier which applied DGS and adaptive bias circuit structure to general Doherty amplifier for the efficiency of a RF power amplifier and a linearity improvement in the WiBro band. As for the IMD3, 3.4dBc was improved with -26.3dBc when we did the measurement result existing Doherty power amplifier and comparison of the Doherty power amplifier which applied an adaptive bias circuit and the DGS which proposed in this paper, and the mean power efficiency verified what was increased in 37%. Also, we were able to know PAE of 36.6% with output power 34.0dBm in P1dB when magnitude of an input signal was 25.6dBm. we did 6dB back off in output P1dB in order to confirm the ACPR which was a nonlinear characteristic and measured the ACPR. we showed the -34.55dBc which was a value of -34.5dBc or below in the 4.77MHz off-set that was a transmission standard. Therefore, we were able to know that we were satisfied with a spectrum mask standard.

• 한국정보통신학회논문지
• /
• 제6권8호
• /
• pp.1297-1304
• /
• 2002

본 논문에서는 저 위상잡음과 고출력 특성을 나타내는 Ku-대역 위상동기발진기를 설계하였다. 발진기소자의 비 선형 파라메터를 분석하여 위상잡음과 발진기출력에 영향을 주는 파라메터의 관계를 최적화시켜 저 위상잡음과 고 출력 특성을 절충되는 바이어스를 구하였다. 위상동기 발진기의 고 안정 특성을 위하여 전치분주형으로 설계하였으며 실험한 결과 위상동기된 상태에서 발진기출력은 10.17dBm이었으며 위상잡음은 13.25GHz에서 10KHz 떨어진 주파수에서 -82d3c/Hz을 보여 10dBm의 출력과 -84dBc/Hz@10KHz에 매우 근접함을 알 수 있었다.

• Journal of information and communication convergence engineering
• /
• 제15권2호
• /
• pp.112-116
• /
• 2017

In this work, we demonstrated a low noise and high linearity low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) with novel active bias circuit for LTE applications. The device technology used in this work relies on a process involving a $0.25-{\mu}m$ GaAs pseudomorphic high electron mobility transistor (PHEMT). The LNA MMIC with a novel active bias circuit has a small signal gain of $19.7{\pm}1.5dB$ and output third order intercept point (OIP3) of 38-39 dBm in the frequency range 1.75-2.65 GHz. The noise figure (NF) is less than 0.58 dB over the full bandwidth. Compared with the characteristics of the LNA MMIC without using the novel active bias circuit, the OIP3 is improved about 2-3 dBm. The small signal gain and NF showed no significant change after using the active bias circuit. The novel active bias circuit indeed improves the linearity performance of the LNA MMIC without degradation.

• 한국통신학회논문지
• /
• 제27권5C호
• /
• pp.530-534
• /
• 2002

본 논문에서는 발진기의 안정도를 높이기 위해 2차 고조파를 병렬 궤환하는 새로운 구조로 자체 위상고정의 효과를 나타낼 수 있도록 제안하였다. 이 구조는 Hair-Pin 공진 발진기를 사용한 대역통과 여파기, 방향성 결합기, 기본주파수 발진기, 체배기, 그리고 출력전력의 궤환 및 격리를 위한 Wilkinson 전력분배기로 구성되었다. 제안된 발진기는 19.5GHz에서 2.5dBm의 출력을 나타내었으며 기본 주파수 억압 -25 dBc, 위상잡음은 중심주파수 19.5 GHz의 10 kHz offset 지점에서 -76.52 dBc/Hz의 안정된 특성을 얻었다.

• 전자공학회논문지C
• /
• 제34C권11호
• /
• pp.66-75
• /
• 1997

We derive the system design parameters to implement the receiving system for the PCS mobile station to satisfy the J-sTD-018 which is the PCS mobile station(MS) minimum performance. Also we analyze the system performance and intermodulation spurious due to the values of a device cause the system performance degradation, is proposed. The simulation shows the receiver's maximum system noise figure to satisfy the receiver selectivity is approximately 11 dB. While the MS noise figure is 10dB with system margin 1 dB, the minimum selectivity is -71 dB at 1.25MHz frequency offset from the carrier frequency. And the input 3rd order intercept point of the MS class I and the MS class II~V is -9.5 dBm and -14dBm respectively. When the interference power level at the receiver is small, the receiver has better performance as we increase the gain of the LNA. However, when the interference level at the receiver is large, the receiver performance is heavily affected by the spurious as we increase the gain of the LNA. Thus, we proved the effectiveness of the LNA On/Off switching technique as to reduce the effect of the spurious.

• 식물조직배양학회지
• /
• 제25권5호
• /
• pp.323-327
• /
• 1998

페튜니아에서의 안토시아닌 생합성 경로는 하나의 중요한 유전적인 모델시스템으로 연구되어 왔다. 본 연구에서는 이 경로에 대한 유전자를 연구하기 위하여 CaMV 35S promoter와 가지로부터 분리된 flavonoid 3',5'-hydroxylase cDNA를 pBI121 플라스미드에서 fusion gene 시스템을 만들었다. 형질전환된 페튜니아를 얻기 위한 최적조건이 페튜니아 절간을 IAA 0.2 ㎎/mL, BA 3 ㎎/mL를 혼용한 MS배지에서 얻었다. 효과적인 형질전환을 위하여 페튜니아 절간을 IAA 0.2㎎/L BA 3㎎/L를 혼용한 BM배지에서 Agrobacterium tumefaciens를 접종하기 전에 절편체를 preculture하였다 형질전환체는 50㎎/L kanamycin과 cefotaxim 300㎎/L을 포함하는 배지에서 선발하였다. PCR과 Southern hybridization분석에 의하여 형질전환체를 검증하였다.

• 한국전기전자재료학회논문지
• /
• 제21권4호
• /
• pp.321-328
• /
• 2008

In this paper, variable gain amplifier(VGA) with a gain slope controller has been proposed and verified by circuit simulations and measurements. The proposed VGA has a gain control, gain slope switch and variable gain range. The input source coupled pair with diode connected load is used for VGA gain stage. The gain slope controller with switch can control VGA gain slope. The proposed VGA is fabricated in $0.18{\mu}m$ CMOS process for multi -standard wireless receiver. The proposed two stage VGA consumes min. 2.0 mW to max. 2.6 mW in gain control range and gives input IP3 of -3.77 dBm and NF of 28.7 dB at 1.8 V power supply under -25 dBm, 1 MHz input. The proposed VGA has 37 dB(-16 dB $\sim$ 21 dB) variable gain range, and 8 dB gain range control per 0.3 V control voltage, and can provide variable gain, positive and negative gain slope control, and gain range control. This VGA characteristics provide design flexibility in multi-standard wireless receiver.