• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• Journal of the Korea Institute of Military Science and Technology
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• v.5 no.2
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• pp.123-131
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• 2002

ASC(Avionics System Computer) was developed to control weapon delivery and navigation sensors, and to perform man-machine interface with pilots for XKO-1 aircraft. The data communications between ASC and UFC(Up Front Controller), DC(Data Concentrator) were implemented by RS422 serial data bus. Also, SCIL(Standard Computer Interface Library) was designed to facilitate control and management of the computer hardware resources and is embedded in the ASC. These structures have a merit of noise immunity and a reduction of wire harness for signal lines, and enable OFP(Operational Flight Program) programmers to use the SCIL easily without knowing hardware details. Manufactured system was on installed on XKO-1, and peformed for BIT(Built In Test) and interface test with UFC and DC. The test results show that it meets the system requirements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.55-62
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• 2012

The development of memory design and process technology enabled the production of high density memory. As the weight of embedded memory within aggregate Systems-On-Chips(SoC) gradually increases to 80-90% of the number of total transistors, the importance of testing embedded dual-port memories in SoC increases. This paper proposes a new micro-code based programmable memory Built-In Self-Test(PMBIST) architecture for dual-port memories that support test various test algorithms. In addition, various test algorithms including March based algorithms and dual-port memory test algorithms are efficiently programmed through the proposed algorithm instruction set. This PMBIST has an optimized hardware overhead, since test algorithm can be implemented with the minimum bits by the optimized algorithm instructions.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06c
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• pp.241-243
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• 2006

소프트웨어의 재사용으로 인한 생산성 향상을 기대하면서, 컴포넌트 기반 개발(Component Based Development)에 관련한 연구가 지속적으로 이루어지고 있으며, 그 중 컴포넌트의 테스트 연구는 컴포넌트를 배포하고, 재사용하기 위해 검증하는데 기여하며 발전해 왔다. BIT(Built-In Test)와 컴포넌트 테스트를 위한 래퍼 클래스에 관한 연구가 대표적이다. 본 논문에서는 테스트 모듈의 산재를 방지하고, 유지보수성과 추적성 개선을 위해 테스트 프로세저를 모듈화하는 방안을 연구하였으며, 이를 위해 관점 지향 프로그래밍 개념을 도입하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.781-792
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• 2016

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures $600{\mu}s$ at 1.1 V and $85^{\circ}C$, enhancing by % over the conventional design approach.

• Proceedings of the Korean Society of Computer Information Conference
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• 2010.07a
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• pp.203-207
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• 2010

In this paper, The design and implementation of Multi Channel Receiver is described in this paper. This Receiver system operates at X-band with processing received signal, more than 80[dB] dynamic range and wide-band signals at the same time. To process direct received signals, this system has the built-in Digital De-modulators which offer the minimum loss on the receiving signal pass and has high stability by adding Built-In Test (BIT). The performance of Multi Receiver is the following. The gain, noise figure, difference of amplitude and phase on the signal pass is respectively $14{\pm}2[dB]$, 19[dB], ${\pm}2[dB]$, and $10^{\circ}$ below.

• Journal of Advanced Navigation Technology
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• v.22 no.2
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• pp.57-63
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• 2018

In the case of aircraft-launched guided weapons, various interface tests such as MIL-STD-1760 based power source, discrete signal, MUX communication as well as BIT of missile can verify system safety and reliability. The purpose of this case study is to develop a test bench based on MIL-STD-1760E for interoperability testing between aircraft and weapons. We proposed a testing method of the launch sequence based on the defined TIME LINE in the development phase of the missile system from the application of the power of the missile to the targeting, the transfer order, and the missile separation process. Furthermore, it will be a reference model that can maximize the verification scope in the development phase of the air to surface missile system by simulating abnormal situation to the inert missile using the error insertion function.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.13-22
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• 1998

In this paper, we propose a high-performance BICS(built-in current sensor) which is fabricated in 0.8${\mu}{\textrm}{m}$ single-poly two-metal process for IDDQ testing of CMOS VLSI circuit. The CUT(circuit under test) is 4-bit full adder with a bridging fault. Using two nMOSs that have different size, two bridging faults that have different resistance values are injected in the CUT. And controlling a gate node, we experimented various fault effects. The proposed BICS detects the faulty current at the end of the clock period, therefore it can test a CUT that has a much longer critical propagation delay time and larger area than conventional BICSs. As expected in the HSPICE simulation, experimental results of fabricated chip demonstrated that the proposed BICS can exactly detect bridging faults in the circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.61-71
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• 2014

As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.1
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• pp.108-114
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• 2021

AVTE(Air Vehicle Test Equipment) is a device to check status of on-board aircraft equipment before and after flight for performing successful UAV(Unmanned Aerial Vehicle) missions. This paper describes software design and test sequence of the AVTE for enabling easy-manual check by the operator and convenient automatic check of on-board electric equipment respectively. The proposed AVTE inspects BIT(Built-In Test) results of on-board LRUs(Line Replacement Units) including avionics and sensor sub-system devices. Also, it monitors all the LRU status and check the normality of aircraft equipment by means of setting specific values of the LRUs and confirming the expected test results. The AVTE prints the test results as a form of report to easily check the normal conditions of the aircraft equipment and operates automatically without operator interaction, thus being thought to effectively reduce workload of the operator.