• 제어로봇시스템학회논문지
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• 제7권3호
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• pp.246-254
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• 2001

In this paper, we described an approach to the automation of visual inspection of BGA solder joint defects of surface mounted components on printed circuit board by using neural network. Inherently, the BGA solder joints are located underneath its own package body, and this induces a difficulty of taking good image of the solder joints by using conventional imaging systems. To acquire the cross-sectional image of BGA sol-der joint, X-ray cross-sectional imaging method such as laminography and digital tomosynthesis has been cur-rently utilized. However, the cross-sectional image obtained by using laminography or DT methods, has inher-ent blurring effect and artifact. This problem has been a major obstacle to extract suitable features for classifi-cation. To solve this problem, a neural network based classification method is proposed int his paper. The per-formance of the proposed approach is tested on numerous samples of printed circuit boards and compared with that of human inspector. Experimental results reveal that the method provides satisfactory perform-ance and practical usefulness in BGA solder joint inspection.

• 마이크로전자및패키징학회지
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• 제9권4호
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• pp.61-68
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• 2002

지금까지 전자 디바이스의 솔더접합부에 대한 신뢰성 평가에 있어서는 열충격시험에 의한 평가가 주류를 이루었다. 그러나 최근 모바일 제품이 소형화/다기능화되고 고밀도실장에 대한 요구가 증가함에 따라 BGA/CSP와 같은 솔더볼을 사용하는 패키지가 표면실장의 주류를 이루게 되었으며, 솔더접합부에 대한 메커니컬 스트레스 수명이 요구되어지고 있다. BGA/CSP의 솔더접합부에 대한 신뢰성 평가는 하중을 가한 상태에서 데이지체인 패턴의 전기적 저항변화와 스트레인 게이지에 의한 스트레스-스트레인 커브에 의해 행해진다. 본 연구에서는 자체 개발한 PCB만능시험장치의 응용과 솔더접합부에 대한 메커니컬 스트레스의 동적거동을 평가한 소니의 실험자료를 소개하도록 한다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.219-225
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• 2002

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2005년도 춘계학술발표대회 개요집
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• pp.19-21
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• 2005

The ball shea. tests for ball grid array (BGA) and flip chip packages were carried out with different displacement rates to find out the optimum condition of the displacement rate for this test. The BGA packages consisted of two different kinds of solder balls (eutectic Sn-37wt.%Pb and Sn-3.5wt.%Ag) and electroplated Au/Ni/Cu substrate, whereas the flip chip package consisted of electroplated Sn-37Pb solder and Cu UBM. The packages were reflowed up to 10 times, or aged at 443 K up to 21 days. The variation of the displacement rate resulted in the variations of the shear properties such as shear force, displacement rate at break, fracture mode and strain rate sensitivity. The increase in the displacement rate led to the increase of the shear force and brittleness of solder joints.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2005년도 춘계학술발표대회 개요집
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• pp.31-33
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• 2005

In this study, the interfacial reactions and electrical properties of the Sn-35(wt%)Pb-2(wt%)Ag/Cu BGA solder joints after the thermal shock test were investigated with three different kinds of the underfill used commercially. The microstructural evolutions of the solder joints were observed using a scanning electron microscopy (SEM) and the electrical resistance of the solder joints were evaluated with the numbers of thermal shock cycle using the four-prove method. The increase in the $Cu_{6}Sn_{5}$ IMC thickness led to the increase in the electrical resistance with increasing the numbers of the thermal shock cycle. The increase in the electrical resistance of the BGA packages with the underfill was smaller than that without the underfill. The silica contained underfill led to the higher electrical resistance.

• 마이크로전자및패키징학회지
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• 제9권2호
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• pp.1-9
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• 2002

실제 BGA패키지에서 Sn-Ag-(Cu) 솔더와 금속패드가 반응하여 생성된 금속간 화합물의 특성을 Scanning Electron Microscopy (SEM), Energy Dispersive Spectroscopy (EDS)f) X-ray Diffractometer (XRD)를 사용하여 분석하였다. EDS로 분석한 결과를 보면 BGA 패키지에서 Sn-Ag-Cu 솔더와 Au/Ni/Cu 금속층간의 반응으로 생성된 금속간화합물은 $(Cu,Ni)_6Sn_5$로 예상되며 . Cu의 편석은 솔더와 Ni 층 사이에서 발견되었다. XRD 분석결과 Cu를 함유하고 있는 Sn-Ag-Cu 솔더와 Ni층 사이에서는 $\eta -Cu_6 Sn_5$ 타입의 금속간화합물이 분석되었으며 Sn-Ag 솔더와 Ni층 사이에서는 $Ni_3$Sn_4$가 분석되었다. 계면에 생성된 금속간화합물은 리플로 회수와솔더내의 Cu의 함량에 따라증가하였다

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 3rd Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.121-145
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• 2001

Chip Size Packages (CSP) are now widely used in high speed DRAM. The major driving farce of CSP development is its superior electrical performance than that of conventional package. However, the power dissipation of high speed DRAM like DDR or RAMBUS DRAM chip reaches up to near 2W. This fact makes the thermal management methods in DRAM package be more carefully considered. In this study, the thermal performances of 3 type CSPs named $\mu-BGA$^{TM}$$ $UltraCSP^{TM}$ and OmegaCSP$^{TM}$ were measured under the JEDEC specifications and their thermal characteristics were of a simulation model utilizing CFD and FEM code. The results show that there is a good agreement between the simulation and measurement within Max. 10% of $\circledM_{ja}$. And they show the wafer level CSPs have a superior thermal performance than that of $\mu-BGA.$ Especially the analysis results show that the thermal performance of wafer level CSPs are excellent fur modulo level in real operational mode without any heat sink.

• Journal of Welding and Joining
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• 제19권3호
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• pp.311-316
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• 2001

This paper presents that the affecting factors to the solderability and initial reliability. It is the factor that the coefficient of thermal expansion between package and PCB(Printed Circuit Board), the quantity of solder paste and reflow condition, and Au thickness of the solder ball pad on polyimide tape. As the reflow soldering condition for 48 ${\mu}BGA$ is changed, it is estimated that the quantity of Au diffusion at eutectic Sn-Pb solder surface and initial bonding strength of eutectic Sn-Pb solder and lead free solder. It is the result that quantitative measurement of Au diffusion quantity is difficult, but the shear strength of eutectic Sn-Pb solder joint is 842 mN at first reflow and increases 879 mN at third reflow. The major failure mode in solder is judged solder fracture. So, Au diffusion quantity is more affected by reflow temperature than by the reflow times.

• 대한금속재료학회지
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• 제46권2호
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• pp.80-87
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• 2008

Many researches related to the reliability of Pb-free solder joints with PCB (printed circuit board) surface finish under thermal or vibration stresses are in progress, because the electronics is operating in hash environment. Therefore, it is necessary to assess Pb-free solder joints life with PCB surface finish under thermal and mechanical stresses. We have investigated 4-points bending fatigue lifetime of Pb-free solder joints with OSP (organic solderability preservative) and ENIG (electroless nickel and immersion gold) surface finish. To predict the bending fatigue life of Sn-3.0Ag-0.5Cu solder joints, we use the test coupons mounted 192 BGA (ball grid array) package to be added the thermal stress by conducting thermal shock test, 500, 1,000, 1,500 and 2,000 cycles, respectively. An 4-point bending test is performed in force controlling mode. It is considered that as a failure when the resistance of daisy-chain circuit of test coupons reaches more than $1,000{\Omega}$. Finally, we obtained the solder joints fatigue life with OSP and ENIG surface finish using by Weibull probability distribution.

• Journal of Welding and Joining
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• 제20권2호
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• pp.90-94
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• 2002

FC-BGA has advantages over other interconnection methods including high I/O counts, better electrical performance, high throughput, and low profile. But, FC-BGA has a lot of reliability issues. The 2nd level solder joint reliability of the FC-BGA with large chip on laminate substrate was studied in this paper. The purpose of this study is to discuss solder joint failures of 2nd level thermal cycling test. This work has been done to understand the influence of the structure of package, the properties of underfill, the properties and thickness of bismaleimide tiazine substrate and the temperature range of thermal cycling on 2nd level solder joint reliability. The increase of bismaleimide tiazine substrate thickness applied to low modulus underfill was improve of solder joint reliability. The resistance of solder ball fatigue was increased solder ball size in the solder joints of FC-BGA.