• Journal of Digital Contents Society
• /
• v.17 no.6
• /
• pp.461-469
• /
• 2016

A novel steganography based on ternary BCH code with t = 2 is presented in this paper. Proposed method utilizes powerful BCH code with t = 2 for data hiding to the DCT coefficients from JPEG images. The presented data hiding technique uses a proposed look up table approach for searching multiple solutions for ternary BCH code with t = 2. The proposed look up table approach enables fast and efficient search for locations of DCT coefficients, which are necessary to modify for hiding data. Presented data hiding technique is the first steganography technique based on ternary BCH code. Experimental results clearly indicate advantages of using ternary BCH compared to binary BCH.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.3 no.4
• /
• pp.737-745
• /
• 1999

In this paper, we present encoders and decoders with the two kinds of ternary Bose-Chaudhuri-Hocquenghem(BCH) codes in the most basic ternary code system from among multiple-valued code systems. One is the random-triple-error-correcting ternary BCH(26,14) code for sequential data, the other is random-triple -error-correcting ternary BCH (26,13) code. The encoders and the decoders realized are verified by experiment. Amount of the (26,13) decoder's hardware is about 50% of the one of the (26,14) decoder's one.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
• /
• 1998.12a
• /
• pp.537-545
• /
• 1998

This paper is the research about a joint coding system of source and channel coding using VF(Variable-to-fixed length) arithmetic code and BCH code. We propose a VF arithmetic coding method with EDC( Error Detecting Capability) and a joint coding method in that the VF arithmetic coding method with EDC is combined with BCH code. By combining both the VF arithmetic code with EDC and BCH code. the proposed joint coding method corrects a source codeword with t-errors in decoding of BCH code and carries out a improvement of the EDC of a codeword with more than (t＋1)-errors in decoding of the VF arithmetic coding with EDC. We examine the performance of the proposed method in terms of compression ratio and EDC.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.05a
• /
• pp.485-488
• /
• 2009

The class of BCH codes is a large class of error correction codes. HDL implementation of BCH code generator to change code rate. and used System Generator, and implemented hardware to FPGA. Loaded bit stream to a FPGA board in order to verify this design to Hardware co-simulation from these results. Also, compared as investigated the maximum action frequency through timing analysis and resource of logic in order to evaluate performance of BCH code generator.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.47 no.6
• /
• pp.1-7
• /
• 2010

This paper presents a novel implementation on multimedia fingerprinting algorithm based on BCH (Bose-Chaudhuri-Hocquenghem) code. The evaluation is put in force the colluder detection to n-1. In the proposed algorit hm, the used collusion attacks adopt logical combinations (AND, OR and XOR) and average computing (Averaging). The fingerprinting code is generated as below step: 1. BIBD {7,4,1} code is generated with incidence matrix. 2. A new encoding method namely combines BIBD code with BCH code, these 2 kind codes are to be fingerprinting code by BCH encoding process. 3. The generated code in step 2, which would be fingerprinting code, that characteristic is similar BCH {15,7} code. 4. With the fingerprinting code in step 3, the collusion codebook is constructed for the colluder detection. Through an experiment, it confirmed that the ratio of colluder detection is 86.6% for AND collusion, 32.8% for OR collusion, 0% for XOR collusion and 66.4% for Averaging collusion respectively. And also, XOR collusion could not detect entirely colluder and on the other hand, AND and Averaging collusion could detect n-1 colluders and OR collusion could detect k colluders.

• International Journal of Contents
• /
• v.9 no.1
• /
• pp.33-37
• /
• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• Journal of Korea Society of Industrial Information Systems
• /
• v.7 no.2
• /
• pp.1-5
• /
• 2002

In this paper, a concatenated turbo and BCH coding is proposed for the wireless ATM cell transmission and the bit error rate(BER) and the cell loss ratio(CLR) for the Nosed system is obtained. Turbo code with code rate of 1/2 and BCH code with error correction capability of 5 and 15 bits are used in the simulations. It is shown that the proposed system obtained about 0.2 and 0.4 ㏈ gain over the conventional Turbo code at bit error rate of 0.001. Also the proposed system obtained about 0.1 and 0.2 ㏈ gain over the conventional Turbo code at cell loss rate of 0.01.

• The KIPS Transactions:PartC
• /
• v.11C no.1
• /
• pp.109-114
• /
• 2004

A new code and its decoding scheme are proposed. With this code, we can correct and detect the errors in communication systems. To limit the runlength of data 0 and augment the minimum density of data 1, a (15, 7) BCH code is modified and an overall parity bit is added. The proposed code is a (16, 7) block code which has the bit clock signal regeneration capability and high error control capability. It is proved that the runlength of data 0 is less than or equal to 7, the density of data 1 is greater than or equal to 1/8, and the minimum Hamming distance is 6. The decoding error probability, the error detection probability and the correct decoding probability are presented for the proposed code. It is shown that the proposed code has better error control capability than the conventional schemes.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.2
• /
• pp.333-340
• /
• 2018

This paper introduces a BCH code decoder using parallel CRC(: Cyclic Redundancy Check) generation. Using a conventional parallel syndrome generator with a LFSR(: Linear Feedback Shift Register), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in $0.35-{\mu}m$ CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.11C
• /
• pp.712-719
• /
• 2011

In this paper, we analyzed the performance of soft decision e-BCH codes which presented in DVB-RCS NG system. However, the performance of soft-decision decoding for e-BCH is not much improved as to increase the iterations. Therefore this paper proposed rate-compatible TPC which makes various coding rates by zero padding the row and/or column to adapt next generation (NG) DVB-RCS system. And so we proposed new model of extended BCH code and researches how to develop performance of extended BCH code.