• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.802-809
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• 2014

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a $0.18-{\mu}m$ CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peak-to-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.

• ETRI Journal
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• 제27권5호
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• pp.473-483
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• 2005

In this paper, we propose two LC voltage-controlled oscillators (VCOs) that improve both phase noise and tuning range. With both 1/f induced low-frequency noise and low-frequency thermal noise around DC or around harmonics suppressed significantly by the employment of a current-current negative feedback (CCNF) loop, the phase noise in the CCNF LC VCO has been improved by about 10 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise of the CCNF VCO was measured as -112 dBc/Hz at 6 MHz offset from 5.5 GHz carrier frequency. Also, we present a bandwidth-enhanced LC VCO whose tuning range has been increased about 250 % by connecting the varactor to the bases of the cross-coupled pair. The phase noise of the bandwidth-enhanced LC-tank VCO has been improved by about 6 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise reduction has been achieved because the DC-decoupling capacitor Cc prevents the output common-mode level from modulating the varactor bias point, and the signal power increases in the LC-tank resonator. The bandwidth-enhanced LC VCO represents a 12 % bandwidth and phase noise of -108 dBc/Hz at 6 MHz offset.

• Journal of Korea Society of Industrial Information Systems
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• 제18권5호
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• pp.9-14
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• 2013

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제37권4A호
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• pp.214-218
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• 2012

In this paper, we reported on a high performance waveguide VCO(voltage controlled oscillator) for FMCW applications. The waveguide VCO consists of a GaAs Gunn diode, a varactor diode, and two bias posts with low pass filter(LPF). The cavity is designed for fundamental mode at 47 GHz and operated at second harmonic of 94 GHz center frequency. The developed waveguide VCO has 1.095 GHz bandwidth, 590 MHz linearity with 1.69% and output power from 14.86 to 15.93 dBm. The phase noise is under -95 dBc/Hz at 1 MHz offset.

• Journal of Korean Society for Atmospheric Environment
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• 제26권4호
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• pp.380-391
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• 2010

Airborne in-situ measurements of aerosol/cloud number concentrations were analyzed to investigate the effects of aerosols on warm cloud formation in the Pacific Dust Experiment (PACDEX) during April and May 2007. In the air masses originating from the Asian continent, high concentrations of fine particles including black carbon (BC) were observed when compared to other regions. A strong correlation (r=0.88) between condensation nuclei (CN) having sizes ranging from 0.1 to 1.0 mm ($CN_{0.1-1.0}$) and cloud condensation nuclei (CCN) at 0.4% supersaturation ($CCN_{0.4%}$) suggests that most of the $CN_{0.1-1.0}$ can contribute to cloud formation. The possibility of a cloud droplet formation by BC particles was expected at the high water vapor mixing ratio (WVMR) and the abundance of water-soluble components at the low altitude less than 3 km.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제16권5호
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• pp.1035-1039
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• 2012

In this paper, we developed a 94 GHz waveguide VCO(voltage controlled oscillator) using a GaAs-based Gunn diode and a varactor diode. The cavity is designed for fundamental mode at 47 GHz and operated at second harmonic of 94 GHz. Bias posts for diodes operate as LPF(low pass filter) and resonator. The fabricated waveguide VCO achieves an oscillation bandwidth of 760 MHz. Output power is from 12.61 to 15.26 dBm and phase noise is -101.13 dBc/Hz at 1 MHz offset frequency from the carrier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제11권4호
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• pp.634-641
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• 2000

A switchable VCO for DECT handset is designed and fabricated. In dual mode radios, a single VCO is desired to operate at two different frequencies to meet the requirement of two mode(Tx, Rx). The three design types of switchable VCO are switched resonator VCO, switched mode VCO and dual band VCO. In this paper, we use the switched resonator VCO type using pin diode switch to change the total amount of capacitance in the tank circuit. At the bias condition of 3 V and 13mA, the output power and phase noise are better than6.5dBm and -104dBc/Hz at 25khz offset from the carrier, respectively , across the operating frequency range. From these results, the fabricated switched VCO is applicable to the DECT handset.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제38A권12호
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• pp.1102-1109
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• 2013

Blind interference alignment (BIA) scheme has demonstrated a way of interference alignment (IA) without channel state information at transmitter (CSIT). While it shows superior performance in high signal-to-noise ratio (SNR) regime stemming from the maximal degrees of freedom (DoF) gain, BIA scheme achieves inferior sum-rate performance in low SNR regime. This paper proposes a dual-mode transmission strategy which switches between single user (SU) SISO with receive mode selection and the BIA scheme depending upon the range of SNR. First, we derive a closed-form achievable rate for each transmission-mode. Secondly, we propose a low-complex transmission-mode selection algorithm.

• Journal of electromagnetic engineering and science
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• 제4권4호
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• pp.168-174
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• 2004

A bandwidth-enhanced and phase noise-improved differential LC-tank VCO is proposed in this paper. By connecting the varactors to the bases of the cross-coupled transistors of the proposed LC-tank VCO, its input negative resistance has been widened. Also, the feedback capacitor Cc in the cross-coupling path of the proposed LC-tank VCO attenuates the output common-mode level modulated by the low-frequency noise because the modulated common-mode level jitters the varactor bias point and degrades phase noise. Compared with the fabricated conventional LC-tank VCO, the proposed LC-tank VCO demonstrates $200\;\%$ enhancement in tuning range, and 6 - dB improvement in phase noise at 6 MHz offset frequency from 5.4-GHz carrier. We achieved the phase noise of - 106 dBc/Hz at 6 MHz offset, and $10\;\%$ tuning range from the proposed LC-tank VCO. The proposed LC-tank VCO consumes 12 mA at 2.5 V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.267-273
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• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.