• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.12
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• pp.1644-1651
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• 1995

A data and clock recovery integrated circuit for MAC (Multiplexed Analog Component) TV standard is described. The chip performs the recovery of a system clock from a digitally encoded voice signal, clamping of a video signal for DC-level restoration, and precise gain control of a video signal in the presence of a large amplitude variation. A PLL (Phase Locked Loop) is used for timing recovery and a new gain control circuit is proposed which enhances its accuracy and dynamic range by employing two identical four-quadrant analog multipliers. The chip is designed in full custom with 1.5um BiCMOS technology, and layout verification is completed by post-simulation with the extracted circuit.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.5
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• pp.21-29
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• 1992

This paper proposes a new MAC propocol for high-speed MAN. The proposed protocol is based on the P$_1$-persistent tranmission scheme and each node calculates the transmission probability periodically by using delay information(DI). A window mechanism for the calculation of message delay in each node is proposed to improve the adaptability of the proposed protocol to traffic changes. The capactiy of the proposed protocol is analyzed. The simulation results show that the proposed protocol gives fair message delay under heavy load conditions and, when the transmission speed or distance is increased, the message delay variation of the proposed protocol is less than that of IEEE 802.6 DQDB.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.5
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• pp.404-410
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• 1991

In this paper,a network interface unit of token-passing bus network and its driving software are implemented based on Mini-MAP. This network interface unit performs the function of MAC layer which is responsible for transmission and reception of frames as well as the management of logical ring. The driving software performs the management of data buffer and the report of errors, if ocoured, to the higher layer. Motorola MC68824 of is used as a TBC(Token Bus Controller) and Intel80186 as a CPU for network interface unit. The operation of network interface unit is verified by self-test which checks the functioning of TBC and CPU. In addition each module of driving software is tested to check the functions regarding transmission and reception of frames.

• Korean Journal of Veterinary Service
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• v.41 no.3
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• pp.171-177
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• 2018

Purified bee venom was collected from colonies of honeybees (Apis mellifera L.) using a bee venom collector under sterile conditions and then purified under strict laboratory conditions. Purified bee venom contained $63.9{\pm}5.4%$ melittin, $10.9{\pm}1.6%$ phospholipase A2, and $2.3{\pm}0.3%$ apamin. Purified bee venom has various anti-bacterial, anti-inflammatory and immunostimulating effects. In this study, we evaluated purified bee venom which are mammary gland cells, MAC-T cells are used to increase the synthesis of milk protein. Purified bee venom promoted the proliferation of MAC-T cells at concentrations below $1{\mu}g/mL$, but cytotoxicity at $10{\mu}g/mL$ and above. As a result of the increase in the synthesis of ${\beta}-casein$, a milk protein after treatment with MAC-T cells at a concentration of the bee venom without cytotoxicity, the ${\beta}-casein$ content in the cell culture was increased when treated at a concentration of 1 ng/mL or more. In addition, it was confirmed that purified bee venom significantly increased the expression of bovine ${\beta}-casein$ (bCSNB) mRNA, a ${\beta}-casein$ synthesis gene, at a concentration of 1 ng/mL or more. These results suggest that purified bee venom can be used to increase the production of livestock by ultimately increasing the expression of milk protein.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.778-781
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• 2007

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture protype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6B
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• pp.423-432
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• 2012

We design a control circuit that can switch input power between a rechargeable battery and a sensor communication device (mote) depending on the operating state of a solar cell as well as the active and sleep mode of a sensor MAC protocol. A mote that simply combines a solarcell and a rechargeable battery may die if there is not sunlight long. A battery is recharged if sunlight is sufficient and a device is in a sleep mode, and it supplies power if sunlight is low and the mote is in an active mode. A mote can switch its input power between solar cell and battery depending on the output level of a solar cell. During this switching, a mote may lose its state information due to the reset of a microprocessor by the transient power-off. A capacitor is used to cope with this phenomenon and also supplies power to a mote during a sleep mode. Experimental results show that the solar cell based mote operates in a very stable manner against the lack of sunlight long.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.5
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• pp.260-270
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• 2014

In this paper, we first analyze the delay performance of Dynamic Space-time Subframe (DSTS)-based frame structure which has been proposed to support the real-time service as well as non real-time service, using Ad hoc Self-Organizing Time Division Multiple Access (ASO-TDMA) MAC protocol, especially when transmitting a MAC SDU with two or more MAC PDUs, in a multi-hop ad-hoc maritime communication network. We propose two key transmission schemes: contiguous DSTS reservation which guarantees the end-to-end delay for the multiple PDUs, and adaptive transmission probability control schemes to maximize the system throughput. Our simulation results show that the proposed schemes outperform the system throughput of the existing transmission schemes, while supporting the real-time requirement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.7
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• pp.543-552
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• 2013

For the safety messages in IEEE 802.11p/WAVE vehicles network environment, strict periodic beacon broadcasting requires status advertisement to assist the driver for safety. In crowded networks where beacon message are broadcasted at a high number of frequencies by many vehicles, which used for beacon sending, will be congested by the wireless medium due to the contention-window based IEEE 802.11p MAC. To resolve the congestion, we consider a MAC scheme based on slotted p-persistent CSMA as a simple non-cooperative Bayesian game which involves payoffs reflecting the attempt probability. Then, we derive Bayesian Nash Equilibrium (BNE) in a closed form. Using the BNE, we propose new congestion control algorithm to improve the performance of the beacon rate under saturation condition in IEEE 802.11p/WAVE vehicular networks. This algorithm explicitly computes packet delivery probability as a function of contention window (CW) size and number of vehicles. The proposed algorithm is validated against numerical simulation results to demonstrate its stability.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.65-70
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• 2008

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b${\times}$32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.

• Journal of Advanced Technology Convergence
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• v.2 no.1
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• pp.1-7
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• 2023

Recently, there have been increasing interests in researches to apply wireless communication technologies for smart farm. This paper introduces the problems in the smart farm for the outdoor culture and technical considerations to solve the problems. As candidate technologies, this paper selects LoRa, Sigfox, NB-IoT, and Wi-Fi and then determines that LoRa is a suitable technology based on the CAPEX, coverage, transmission rate, battery, and the price. To provide technical analysis, this paper introduces technologies related to the physical and medium access control (MAC) layers as well as the security. Specifically, this paper includes the modulation technology in the physical layer, Class (Class A, B, and C) based protocol operations in MAC layer, and security architecture based on the LoRa version.