• Journal of the Korea Society of Computer and Information
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• v.22 no.4
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• pp.25-32
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• 2017

Recently, the use of NAND flash memory is being increased as a secondary device to displace conventional magnetic disk. NAND flash memory, as one among non-volatile memories, has many advantages such as low power, high reliability, low access latency, and so on. However, NAND flash memory has disadvantages such as erase-before-write, unbalanced operation speed, and limited P/E cycles, unlike conventional magnetic disk. To solve these problems, NAND flash memory mainly adopted FTL (Flash Translation Layer). In particular, garbage collection technique in FTL tried to improve the system lifetime. However, previous garbage collection techniques have a sensitive property of the system lifetime according to write pattern. To solve this problem, we propose BSGC (Balanced Selection-based Garbage Collection) technique. BSGC efficiently selects a victim block using all intervals from the past information to the current information. In this work, SFL (Search First linked List), as the proposed block allocation policy, prolongs the system lifetime additionally. In our experiments, SFL and BSGC prolonged the system lifetime about 12.85% on average and reduced page migrations about 22.12% on average. Moreover, SFL and BSGC reduced the average response time of 16.88% on average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.18-24
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• 2007

As VLSI technology scales to nano-meter order, relatively increasing global wire-delay has added complexity to system design. Global wire-delay could be reduced by inserting pipeline-elements onto wire but it should be coupled with LIP(Latency Intensive Protocol) to have correct system timing. This combination however, drops the throughput although it ensures system functionality. In this paper, we propose a computation method useful for minimizing throughput deterioration when pipeline-elements are inserted to reduce global wire-delay. We apply this method while placing blocks in the floorplanning stage. When the necessary for this computation is reflected on the floorplanning cost function, the throughput increases by 16.97% on the average when compared with the floorplanning that uses the conventional heuristic throughput-evaluation-method.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.287-299
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• 2000

In this paper, we classify multicast methods into three categories, i.e., tree-based, path-based, and hybrid-based multicasts, for a multicomputer employing the bidirectional torus network and wormhole routing. We propose the dynamic partition multicast routing (DPMR) as a path-based algorithm. As a hybrid-based algorithm, we suggest the hybrid multicast routing (HMR), which employs the tree-based approach in the first phase of routing and the path-based approach in the second phase. Performance is measured in terms of the average latency for various message length to compare three multicast routing algorithms. We also compare the performance of wormhole routing having variable buffer size with virtual cut-through switching. The message latency for each switching method is compared using the DPMR algorithm to evaluate the buffer size trade-off on the performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.174-177
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• 2016

Wireless network-on-chip (WNoC) can alleviate critical path problem of existing typical NoCs by integrating radio-frequency module on router. In this paper, core-connection-aware genetic algorithm-based core and WIR mapping methodology at small world WNoC is presented. The methodology could optimize the critical path between cores with heavy communication. The 33% of average latency improvement is achieved compared to random mapping methodology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9B
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• pp.1266-1271
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• 2010

In this paper, we describe overhead problems which result from the supporting NEMO in PMIPv6 networks, and propose a novel binding scheme for the network-based mobility management with new network-layer message which solves the problems of the additional tunnel. Our proposed binding scheme can reduce handover latency without mobility-related procedure by the hosts. A performance evaluation shows that the proposed scheme works more efficiently than the scheme which is proposed by the IETF NETLMM WG in terms of packet loss, handover latency and average packet throughput.

• ETRI Journal
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• v.31 no.2
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• pp.111-120
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• 2009

Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.321-328
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• 2010

This paper presents a coordinator-based TDMA reader protocol that can avoid the reader collision in a passive RFID system. In the proposed protocol, the coordinator can not only minimize the number of empty slots by efficiently allocating slots to readers incoming in Poisson distribution, but reduce latency time through the limited frame size. The proposed protocol can be implemented in either mobile or fixed mode through the slot structure to be described in the context. The simulation results show it works as suggested and the frame size limitation as well as the statistical distribution of incoming readers has a great impact on the overall slots and the average latency time.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.2
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• pp.383-403
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• 2021

With the development of mobile edge computing (MEC), some late-model application technologies, such as self-driving, augmented reality (AR) and traffic perception, emerge as the times require. Nevertheless, the high-latency and low-reliability of the traditional cloud computing solutions are difficult to meet the requirement of growing smart cars (SCs) with computing-intensive applications. Hence, this paper studies an efficient offloading decision and resource allocation scheme in collaborative vehicular edge computing networks with multiple SCs and multiple MEC servers to reduce latency. To solve this problem with effect, we propose a context-aware offloading strategy based on differential evolution algorithm (DE) by considering vehicle mobility, roadside units (RSUs) coverage, vehicle priority. On this basis, an autoregressive integrated moving average (ARIMA) model is employed to predict idle computing resources according to the base station traffic in different periods. Simulation results demonstrate that the practical performance of the context-aware vehicular task offloading (CAVTO) optimization scheme could reduce the system delay significantly.

• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.1
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• pp.31-40
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• 2023

Recent advances in flash technologies, such as 3D processing and multileveling schemes, have successfully increased the flash capacity. Unfortunately, these technology advances significantly degrade flash's reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose an asymmetric BER-aware reliability optimization technique (aBARO), new flash optimization that improves the flash reliability. To this end, we first reveal that bit errors of 3D NAND flash memory are highly skewed among flash cell states. The proposed aBARO exploits the unique per-state error model in flash cell states by selecting the most error-prone flash states and by forming narrow threshold voltage distributions (for the selected states only). Furthermore, aBARO is applied only when the program time (tPROG) gets shorter when a flash cell becomes aging, thereby keeping the program latency of storage systems unchanged. Our experimental results with real 3D MLC and TLC flash devices show that aBARO can effectively improve flash reliability by mitigating a significant number of bit errors. In addition, aBARO can also reduce the read latency by 40%, on average, by suppressing the read retries.

• International Journal of Computer Science & Network Security
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• v.24 no.4
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• pp.11-25
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• 2024

The proliferation of IoT devices has presented an unprecedented challenge in managing device identities securely and efficiently. In this paper, we introduce an innovative Hybrid Blockchain-Based Approach for IoT Identity Management that prioritizes both security and efficiency. Our hybrid solution, strategically combines the advantages of direct and indirect connections, yielding exceptional performance. This approach delivers reduced latency, optimized network utilization, and energy efficiency by leveraging local cluster interactions for routine tasks while resorting to indirect blockchain connections for critical processes. This paper presents a comprehensive solution to the complex challenges associated with IoT identity management. Our Hybrid Blockchain-Based Approach sets a new benchmark for secure and efficient identity management within IoT ecosystems, arising from the synergy between direct and indirect connections. This serves as a foundational framework for future endeavors, including optimization strategies, scalability enhancements, and the integration of advanced encryption methodologies. In conclusion, this paper underscores the importance of tailored strategies in shaping the future of IoT identity management through innovative blockchain integration.