• 제목/요약/키워드: Average circuit

검색결과 425건 처리시간 0.025초

Millimeter Wave MMIC Low Noise Amplifiers Using a 0.15 ${\mu}m$ Commercial pHEMT Process

  • Jang, Byung-Jun;Yom, In-Bok;Lee, Seong-Pal
    • ETRI Journal
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    • 제24권3호
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    • pp.190-196
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    • 2002
  • This paper presents millimeter wave monolithic microwave integrated circuit (MMIC) low noise amplifiers using a $0.15{\mu}m$ commercial pHEMT process. After carefully investigating design considerations for millimeter-wave applications, with emphasis on the active device model and electomagnetic (EM) simulation, we designed two single-ended low noise amplifiers, one for Q-band and one for V-band. The Q-band two stage amplifier showed an average noise figure of 2.2 dB with an 18.3 dB average gain at 44 GHz. The V-band two stage amplifier showed an average noise figure of 2.9 dB with a 14.7 dB average gain at 65 GHz. Our design technique and model demonstrates good agreement between measured and predicted results. Compared with the published data, this work also presents state-of-the-art performance in terms of the gain and noise figure.

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뇌졸중 환자의 균형 향상 과제 중심 순환 훈련의 효과 (The Effect of Balance Task-Related Circuit Training on Chronic Stroke Patients)

  • 이한숙;김명철
    • The Journal of Korean Physical Therapy
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    • 제21권4호
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    • pp.23-30
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    • 2009
  • Purpose: This study investigated the efficacy of task-related circuit training aimed at improving balance in individuals discharged from rehabilitation facilities following a stroke. Methods: We recruited 12 stroke patients (34-66 years of age) to participate in a task-related circuit training program. Baseline assessment included a history of stroke and an assessment using the Mini-Mental State Examination Korea (MMSE-K). After a baseline assessment, follow-up assessments were administered pre- and post-training. These included Berg Balance Scale (BBS), Functional Reach Test (FRT), and the Time Up & Go Test (TUG). Physiotherapists trained study subjects under the one-to-one supervision of students from the department of physical therapy. Circuit class study participants attended 90-minute treatment sessions, one day a week for 12 weeks (from September to December 2008). The program consisted of a light warm-up period (10 min), physical exercises for improving balance (20 min), tasks focused on improving balance (50 min) and a cool-down period (10 min). Results: Scores for the BBS assessment increased significantly (from 43.2 to 49.7) after the training (p<0.05). Reach distance on the FRT increased substantially (from 27.7 cm to 47.0 cm), although the improvement was not significant (p>0.05). The average time on the TUG test decreased significantly (from 23.7 sec to 19.5 sec) after the training (p<0.05). Conclusion: The task-related circuit training program improved the balance and mobility of subjects, indicating that such a group program is useful for stroke patients who are discharged from the hospital. More such task-related programs set in a community environment should be developed.

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Experimental Investigations Into Low Current Steady State Arcs In A Dual-Airflow Model Interrupter

  • Shin, Young-June;Cho, Yun-Ok;Kim, Jin-Gi;Lee, Jeong-Rim
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1992년도 하계학술대회 논문집 B
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    • pp.961-965
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    • 1992
  • It is well-known that shock waves frequently occur inside the nozzle of the interrupter, and that they play important roles in the arc interruption. A model interrupter with two-dimensional dual-airflow nozzles was used for this experiment. The arc was ignited with 1.4 mil copper wire stretched between the electrodes which were spaced out 56 mm. The arc current of 60 to 230 A was achieved by adjusting the external resistance from 5.5 to 1.6 ohms. The arc tests have been conducted for investigating the air arc characteristics, and the effects of shock waves and nozzle pressure ratios on the arc voltage, the arc resistance, the arc power, and average electric field. The results of these tests have been analyzed to provide insights into the arc characteristics for gas circuit breakers. The average electric field is represented by the function of the arc current to show the negative E-I characteristic explicitly. The effects of shock waves and nozzle pressure ratios are shown to be significant for a circuit breaker performance.

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자동차용 전동시스템 해석을 위한 평균값 인버터 모델 개발 (Development of Average Inverter Model for Analysis of Automotive Electric Drive System)

  • 최진철;배규태;이우택
    • 한국자동차공학회논문집
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    • 제18권6호
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    • pp.23-30
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    • 2010
  • A detailed circuit level model requires a small sampling time to represent high frequency switching behaviors with proper resolution. The small sampling time leads a large execution time to obtain the system analysis results. As the alternative of the detailed circuit model, an averaged PWM switch model was proposed for the rapid system level analysis. There exists a voltage distortion between the reference and output voltage because of non-ideal switching characteristics, such as the dead-time, diode forward voltage drop and conduction resistance. This paper analyzed causes and effects of the voltage distortion. The average inverter model, which reflecting this voltage distortion, is developed for the rapid and accurate analysis of automotive electric drive system in MATLAB/Simulink environment. The rapidity and accuracy of the proposed inverter model is proved through comparison between simulation and experiment.

차량 위치추적기반 교통신호등 제어용 UWB 시스템의 Acquisition 알고리즘 연구 (RASE Acquisition Algorithm of Ultra Wideband System for Car Positioning and Traffic Light Control)

  • 황인관;박윤진
    • 한국통신학회논문지
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    • 제30권10C호
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    • pp.992-998
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    • 2005
  • 본 논문에서는 고정밀 차량위치 추적 기반의 교통신호등 제어를 위한 저전송율 초광대역 무선통신 시스템에서의 Ultra Fast Acquisition 알고리즘을 연구하였다. 현재 CDMA에서 사용되는 acquisition방식으로는 저전송율 UWB시스템에서 회로가 복잡해지고 빠른 acquisition을 기대할 수 없기 때문에 새로운 Ultra Fast Acquisition방식이 필요하다. 기본적으로 Sequential Estimation방식을 사용하며 trinomial m-시퀀스를 사용하여 유비쿼터스 센서 네트워크용 U시스템에서 long PN code를 사용하는 경우에도 회로의 복잡도를 줄이고 FCC Emission limit을 만족시키면서, $1\~3{\mu}sec$이내의 acquisition을 가능하도록 설계하였다.

전류모드 CMOS 4치 논리회로를 이용한 64×64-비트 변형된 Booth 곱셈기 설계 (Design of a 64×64-Bit Modified Booth Multiplier Using Current-Mode CMOS Quarternary Logic Circuits)

  • 김정범
    • 정보처리학회논문지A
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    • 제14A권4호
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    • pp.203-208
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    • 2007
  • 본 논문에서는 CMOS 다치 논리회로를 이용하여 $64{\times}64$ 비트 Modified Booth 곱셈기를 설계하였다. 설계한 곱셈기는 Radix-4 알고리즘을 이용하여 전류모드 CMOS 4치 논리회로로 구현하였다. 이 곱셈기는 트랜지스터 수를 기존의 전압모드 2진 논리 곱셈기에 비해 64.4% 감소하였으며, 내부 구조를 규칙적으로 배열하여 확장성을 갖도록 설계하였다. 설계한 회로는 2.5V의 공급전압과 단위전류 $5{\mu}A$를 사용하여, $0.25{\mu}m$ CMOS 기술을 이용하여 구현하였으며 HSPICE를 사용하여 검증하였다. 시뮬레이션 결과, 2진 논리 곱셈기는 $7.5{\times}9.4mm^2$의 점유면적에 9.8ns의 최대 전달지연시간과 45.2mW의 평균 전력소모 특성을 갖는 반면, 설계한 곱셈기는 $5.2{\times}7.8mm^2$의 점유면적에 11.9ns의 최대 전달지연시간과 49.7mW의 평균 전력소모 특성으로 점유면적이 42.5% 감소하였다.

Average Current Mode Control for LLC Series Resonant DC-to-DC Converters

  • Park, Chang Hee;Cho, Sung Ho;Jang, Jinhaeng;Pidaparthy, Syam Kumar;Ahn, Taeyoung;Choi, Byungcho
    • Journal of Power Electronics
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    • 제14권1호
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    • pp.40-47
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    • 2014
  • An average current mode control scheme that consistently offers good dynamic performance for LLC series resonant DC-to-DC converters irrespective of the changes in the operational conditions is presented in this paper. The proposed control scheme employs current feedback from the resonant tank circuit through an integrator-type compensation amplifier to improve the dynamic performance and enhance the noise immunity and reliability of the feedback controller. Design guidelines are provided for both current feedback and voltage feedback compensation. The performance of the new control scheme is demonstrated through an experimental 150 W converter operating with 340 V to 390 V input voltage to provide a 24 V output voltage.

개선된 영상 보간 알고리즘을 이용한 PCI 인터페이스 설계에 관한 연구 (A Study on the PCI Interface Design using Modified Image Interpolation Algorithm)

  • 이인섭;고영욱;김환용;김태형
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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    • pp.409-412
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    • 2001
  • This paper decides provision of brightness by average value of horizontal pixel, vertical pixel association. Give weight at association value calculation to improve diagonal line characteristics, and applied method to add average of vertical pixel and average of diagonal line pixel at interpolation. Therefore it improves PSNR, and it proposed algorithm that improve horizontal outline and vortical outline characteristics in big area of luminance contrast. It changed scanning line of serial scan based on proposed algorithm and designed variable image system for efficient data transmission through PCI interface circuit.

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3-레벨 PWM 인버터 전류산정에 관한 연구 (A Study on the computation of currents in the three-level PWM inverter)

  • 김광섭;서범석;현동석
    • 대한전기학회논문지
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    • 제45권3호
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    • pp.341-351
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    • 1996
  • The values for the average and rms currents in a three-level PWM inverter are required in order to select the various components such as power semiconductor devices, capacitors and reactors of inverter circuit. And those are very useful for the designing of the heat sink. In this paper, therefore, the simple current equations are proposed for a three-level PWM inverter. Analysis of inverter current waveforms indicate that the average and rms inverter currents are dependent on the load power factor and PWM modulation index (Ma). Error analysis and experiment results verify the effectiveness of the proposed current equations. (author). refs., figs., tabs.

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An Economic Design of a k-out-of-n System

  • Yun, Won-Young;Kim, Gue-Rae;Gopi Chattopadhyay
    • International Journal of Reliability and Applications
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    • 제4권2호
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    • pp.51-56
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    • 2003
  • A k-out-of-n system with n identical and independent components is considered in which the components takes two types of function: 0 (open-circuit) or 1 (closed) on command (e.g. electromagnetic relays and solid state switches). Components are subject to two types of failure on command: failure to close or failure to open. In our k-out-of-n system, failure of (n-k)+1 or more components to close causes to the close failure of the system, or failure of k or more components to open causes the open failure of the system. The long-run average cost rate is obtained. We find the optimal k minimizing the long run average cost rate for given n. A numerical example is presented.

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