• The Journal of Korea Robotics Society
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• v.4 no.1
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• pp.1-9
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• 2009

Radio Frequency Identification (RFID) is an automatic identification method. Information such as identification, logistics history, and specification of products are written and stored into the memory of RFID tags (that is, transponders), and retrieved through RF communication between RFID reader device and RFID tags. RFID systems have been applied to many fields of transportation, industry, logistics, environment, etc in order to improve business efficiency and reduce maintenance cost as well. Recently, some research results are announced in which RFID devices are combined with other sensors for mobile robot localization. In this paper, design of multi-protocol baseband for RFID reader device is proposed, and the baseband modem is implemented into SoC (System On a Chip). The baseband modem SoC for multi-protocol RFID reader is composed of several IP (Intellectual Property) blocks such as multi-protocol blocks, CPU, UART(Universal Asynchronous Receiver and Transmitter), memory, etc. As a result, the SoC implemented with FPGA(Field Programmable Gate Array) is applied to real product. It is shown that the size of RFID Reader module designed with the FPGA becomes smaller, and the SoC chip price for the same function becomes cheap. In addition, operation performance could be the same or better than that of the product with no SoC applied.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1141-1149
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• 2000

This paper proposes new cost error measurement method and analyzes the optimistic and pessimistic cost errors statistically which is resulted from an asynchronous parallel Simulated annealing (SA) in distributed memory multicomputers. The traditional cost error measurement scheme has inherent problems which are corrected in the new method. At each temperature the new method predicts the amount of cost error that an algorithm will tolerate and still converge by the hill-climbing nature of SA. This method also explains three interesting phenomenon of he cost error analytically. So the new cost error measurement method provides a single mechanism for the occurrence of cost error and its control.

• Proceedings of the Korean Society for Language and Information Conference
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• 2007.11a
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• pp.87-94
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• 2007

This paper introduces BEYTrans (Better Environment for Your TRANSlation), the first experimental environment for free online collaborative computer-aided translation. The requirements and functionalities related to individual translators and communities of translators are distinguished and described. These functionalities have been integrated in a Wiki-based complete environment, equipped with all currently possible asynchronous linguistic resources and translation aids. Functions provided by BEYTrans are also compared with existing CAT systems and ongoing experiments are discussed.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1964-1967
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• 2002

Recently design verification have been played an important role in the design of large scale and complex systems. In this article, we especially focus on model checking methods. Behaviors of modeled systems are generally specified by temporal formulas of computation tree logic. However. Users must know well temporal specification because the specification might be complex. We proposed method that temporal formulas are gained inductively and amounts of memory and time are reduced. Finally, we will show verification results using our proposed method.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.533-536
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• 2000

In this paper, we proposed high performance packet forwarding engine for asynchronous transfer mode(ATM) based gigabit routers. The forwarding engine is based on ATM switch and accommodates four 622Mbps ports. The forwarding engine has been designed to be able to process the Intemet protocol(IP) packet at 2.5Gbps using the pipelined If header processing and lookup control mechanism. For high performance packet forwarding, we used content addressable memory(CAM) based routing coprocessor operating in hardware and implemented the pipelined lookup control function into a field programmable gate array(FPGA). The pipelined packet header processing mechanism enhanced the forwarding performance of the If packets ingressed from four different 622Mbps ports. Moreover, the If lookup controller designed to have the performance up to 12.5Mpps. The proposed forwarding engine is also designed to support differentiated services(DS) and multiprotocol label switching(MPLS).

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.8
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• pp.1254-1260
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• 2009

CDMA tele-Controller system is designed with a low power consumption 8 bit microcontroller, ATmega 2560. ATmega 2560 microcontroller consists of 4 UART (Universal asynchronous receiver/transmitter) ports, 4 kbytes EEPROM, 256 kbytes flash memory, 4 kbytes SRAM. 4 URAT is used for CDMA modem, communication for GPS module, EEPROM is used for saving a configuration for program running, a flash memory of 256 kbytes is used for storing a F/W(Firm Ware), and SRAM is used for stack, storing memory of global variables while program running. We have tested the communication distance between the coast station and sea by the fabricated control board using 800 MHz CDMA modem and GPS module, which is building for the navigational aid management system by remote control. As a results, the receiving signal strength is above -80 dBm, and then the characteristics of the control board implemented more than 10 km in the distance of the communication.

• The KIPS Transactions:PartC
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• v.13C no.5 s.108
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• pp.583-594
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• 2006

The reliability concept of wireless sensor network is essential to get exactly actual data from the ubiquitous environment. A rollback technique for the self-healing helps to increase it. However, a fault can occur in wireless sensor network when to use a previous rollback technique because it is designed just for the local system. So, checkpoint protocols are suggested in order to use a rollback technique in the network without the fault. However, there is trade-off among performance overhead, power consumption, and memory overhead for each of protocols. Hence, we suggest a novel global checkpoint protocol, so called address log based protocol(ALBP), based on an asynchronous protocol. It is a platform based protocol to reduce power consumption, performance overhead, and memory overhead which are the most of consideration in wireless sensor network.

• The KIPS Transactions:PartA
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• v.8A no.2
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• pp.107-116
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• 2001

A multithreaded model is a hybrid one which combines locality of execution of the von Neumann model with asynchronous data availability and implicit parallelism of the dataflow model. Much researches that have been made toward the advanced performance of multithreaded models are about the cache memory which have been proved to be efficient in the von Neumann model. To use an instruction cache or operand cache, the multithreaded models must have cache memories. If cache memories are added to the multithreaded model, they may have the disadvantage of high implementation cost in the mode. To solve these problems, we did not add cache memory but applied the method of executing the caching by using available registers of the multithreaded models. The available register-based caching method is one that use the registers which are not used on the execution of threads. It may accomplish the same effect as the cache memory. The multithreaded models can compute the number of available registers to be used during the process of the register optimization, and therefore this method can be easily applied on the models. By applying this method, we can also remove the access conflict and the bottleneck of frame memories. When we applied the proposed available register-based caching method, we found that there was an improved performance of the multithreaded model. Also, when the available-register-based caching method is compared with the cache based caching method, we found that there was the almost same execution overhead.

• The KIPS Transactions:PartD
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• v.17D no.1
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• pp.9-16
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• 2010

Web service mashup bacomes one of the important web application development methods. This paper considers a client based mashup, where a page interfaces many service methods asynchronously. Browser systems execute callbacks when the corresponding reply arrives, possibly concurrent to user interface actions. In this case, callbacks and user interface actions share data memory and screen. Moreover, when the user is able to send another request before the previous ones have replied, the shared resource problem becomes more complicated. In order to solve the multiple requests problem, our contributions are as follows. First, we modeled a mashup page with user actions and callbacks, and we presented several types of callbacks. Secondly, concurrency condition is defined between callbacks and user actions in terms of shared resources, and the test method is presented. Also, we proposed the serialization approach to guarantee the safe execution of callbacks. Finally, we applied the proposed concurrency condition on XForms language and extended the XForms browser to implement the proposed approach. The prototype implementation showed that the proposed approach helps enhancing user experience on mashup pages.

• Convergence Security Journal
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• v.21 no.2
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• pp.29-35
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• 2021

UART (Universal asynchronous receiver/transmitter) is a hardware device that converts data into serial format and transmits it, and is widely used for system diagnosis and debugging in most embedded systems. Hackers can access system memory or firmware by using the functions of UART, and can take over the system by acquiring administrator rights of the system. In this paper, we studied secure UART to protect against hacker attacks through UART. In the proposed scheme, only authorized users using the promised UART communication protocol are allowed to access UART and unauthorized access is not allowed. In addition, data is encrypted and transmitted to prevent protocol analysis through sniffing. The proposed UART technique was implemented in an embedded Linux system and performance evaluation was performed.