• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.235-237
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• 2003

멀티미디어 데이터 전송이 가능한 초고속 통신망의 발달로 음성을 위주로 서비스하던 과거와는 다른 self-similar 특성을 갖는 데이터 트래픽이 발생된다는 것이 알려지고 있다. 이러한 트래픽은 전통적인 네트워크 해석 방법인 포와송 트래픽 모델과는 상당히 차이가 난다는 것이 여러 트래픽의 측정 결과 나타나고 있다. 본 논문에서는 공유 메모리를 갖는 CS(Complete Sharing), DT(Dynamic Threshold), PO(Push-Out) 그리고, SMXQ(Sharing with Maximum Queue)와 같은 다양한 ATM(Asynchronous Transfer Mode) 스위치의 버퍼 관리 기법을 이용하여 입력포트에 self-similar 성질을 갖는 트래픽이 들어올 때 출력포트에서의 self-similarity와 셀 손실률 그리고, 이용률 등을 분석한다.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1177-1180
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• 2005

This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.664-665
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• 2013

This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.617-620
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• 2002

본 논문에서는 single bank와 multi bank FIFO를 지원하는 CMOS FIFO memory compiler를 개발 검증하였다. 이 컴파일러를 사용해서 설계자는 구현하고자 하는 어플리케이션에 적합한 high speed, high density, low power를 갖는 on-chip memory를 빠른 시간에 만들어 낼 수 있으므로 설계 시간을 절약할 수 있다. 이와 더불어 설계된 FIFO 의 시뮬레이션을 지원하기위한 Verilog 시뮬레이션 모델을 제공하였다. 현재 FIFO를 구성하는 단위 셀들은 0.6um 3-metal 공정을 이용하여 설계하였으며 공정의 변화에 따라 대상 공정에 맞도록 단지 몇 개의 단위 셀만을 재 설계하고 그에 대한 정보를 갱신해줌으로써 공정의 변화에 대처 할 수 있도록 하였다. 설계된 컴파일러를 이용해 생성된 FIFO 는 표준 셀 라이브러리를 이용한 합성 가능한 FIFO에 대하여 $16bit{\times}16word$ FIFO에서 면적면에서 93%, 속도면에서 70%의 향상을 보였다.

• Journal of KIISE:Databases
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• v.29 no.6
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• pp.492-501
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• 2002

An asynchronous trigger processor (ATP) is a oftware system that processes triggers after update transactions to databases are complete. In an ATP, discrimination networks are used to check the trigger conditions efficiently. Discrimination networks store their internal states in memory nodes. TriggerMan is an ATP and uses Gator network as the .discrimination network. The changes in databases are delivered to TriggerMan in the form of tokens. Processing tokens against a Gator network updates the memory nodes of the network and checks the condition of a trigger for which the network is built. Parallel token processing is one of the methods that can improve the system performance. However, uncontrolled parallel processing breaks trigger processing semantic consistency. In this paper, we propose four trigger processing consistency levels that allow parallel token processing with minimal anomalies. For each consistency level, a parallel token processing technique is developed. The techniques are proven to be valid and are also applicable to materialized view maintenance.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1675-1689
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• 2000

We present CReMeS a CORBA-compliant design and implementation of a new real-time communication service. It provides for efficient predictable and scalable communication between information producers and consumers. The CReMeS architecture is based on MidART's Real-Time Channel-based Reflective Memory (RT-CRM) abstraction. This architecture supports the separation of QoS specification between producer and consumer of data and employs a user-level scheduling scheme for communicating real-time tasks. These help us achieve end-to-end predictability and allows our service to scale. The CReMeS architecture provides a CORBA interface to applications and demands no changes to the ORB layer and the language mapping layer. Thus it can run on non real-time Off-The-Shelf ORBs enables applications on these ORBs to have scalable and end-to-end predictable asynchronous communication facility. In addition an application designer can select whether to use an out-of-band channel or the ORB GIOP/IIOP for data communication. This permits a trade-off between performance predictability and reliability. Experimental results demonstrate that our architecture can achieve better performance and predictability than a real-time implementation of the CORBA Even Service when the out-of-band channel is employed for data communication it delivers better predictability with comparable performance when the ORB GIOP/IIOP is used.

• Nuclear Engineering and Technology
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• v.48 no.3
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• pp.635-641
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• 2016

Because of prohibitive data storage requirements in large-scale simulations, the memory problem is an obstacle for Monte Carlo (MC) codes in accomplishing pin-wise three-dimensional (3D) full-core calculations, particularly for whole-core depletion analyses. Various kinds of data are evaluated and quantificational total memory requirements are analyzed based on the Reactor Monte Carlo (RMC) code, showing that tally data, material data, and isotope densities in depletion are three major parts of memory storage. The domain decomposition method is investigated as a means of saving memory, by dividing spatial geometry into domains that are simulated separately by parallel processors. For the validity of particle tracking during transport simulations, particles need to be communicated between domains. In consideration of efficiency, an asynchronous particle communication algorithm is designed and implemented. Furthermore, we couple the domain decomposition method with MC burnup process, under a strategy of utilizing consistent domain partition in both transport and depletion modules. A numerical test of 3D full-core burnup calculations is carried out, indicating that the RMC code, with the domain decomposition method, is capable of pin-wise full-core burnup calculations with millions of depletion regions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• Journal of Advanced Navigation Technology
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• v.23 no.5
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• pp.452-459
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• 2019

In this paper, we describe a PCM encoder structure that can update the telemetry system parameters in real time. In the PCM encoder, an analog signal control unit for FPGA, flash memory, and sensor data acquisition was constructed. UART communication, analog signal control, flash memory control, and frame generation are possible through logic inside FPGA of PCM encoder. UART communication allows the PC to transmit parameter data to the PCM encoder, and flash memory is controlled to update the parameter of the telemetry system in real time and finally the frame is formed. Simulation and verification were performed to confirm whether the parameter data is updated in real time, and the proposed structure was used to construct a telemetry system with enhanced flexibility and convenience.