• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.325-328
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• 2001

In this work, Cell search which is one of the important abilities of W-CDMA system in Reyleigh s fading channel is studied by using Cell Searcher of asynchronous IMT-2000 system(3GPP) and Cell - search simulation. For the methods of cell search to optimize codes, three stages are considered: 1) slot synchronization, 2) frame synchronization, and 3) scrambling code identification. It is found that key system parameters such as Primary Synchronization Channel (P-SCH), Secondary L Synchronization Channel(S-SCH), and Common Pilot Channel (CPCH) loading factor are optimized. It is noted that the smaller Optimal threshold value, the larger SNR of the received singnal. Therefore, It is important that the optimal threshold value is selected in the region of SNR

• Journal of Advanced Navigation Technology
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• v.27 no.6
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• pp.884-887
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• 2023

Recently, research has been actively conducted to overcome the limitations of high-priced single sensors and reduce costs through the convergence of low-cost multi-variable sensors. This paper estimates state variables through asynchronous Kalman filters constructed using CVXPY and uses Cvxpylayers to compare and learn state variables estimated from CVXPY with true value data to estimate filter parameters of low-cost sensors fusion.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.182-189
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• 2010

This paper defines the quorum-based fault-tolerant mutual exclusion problem in a message-passing asynchronous system and determines a failure detector to solve the problem. This failure detector, which we call the modal failure detector star, and which we denote by $M^*$, is strictly weaker than the perfect failure detector P but strictly stronger than the eventually perfect failure detector ◇P. The paper shows that at any environment, the problem is solvable with $M^*$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1380-1386
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• 2011

The request of interrupt accompanies a context switching. If the interrupt is frequently requested, this overhead of context switching can reduce seriously the performance of embedded systems. In order to reduce processing overhead due to frequently requested communication interrupts at Asynchronous Serial Communication, this paper introduces the method of Expanded Asynchronous Serial Communication with the Interrupt Coalescence(IC) that accumulates a fixed number of interrupts and processes them in one time. we implement the existing Asynchronous Serial Communication that requests communication interrupts by one byte at an LN2440SBC embedded board with a uC/OS-II and compare interrupt processing time for the performance evaluation about proposed method. As a result, the communication interrupt processing time of proposed method appears in case of low speed(9,600 bps), the decline of an average 25.18% at transmission, the decline of an average 41.47% at reception. and in case of hight speed(115,200 bps), the decline of an average 16.67% at transmission, the decline of an average 25.61% at reception.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.17-25
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• 2016

This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.3
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• pp.399-408
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• 2022

This paper proposes a corrective control system to achieve fault-tolerant control for input/output asynchronous sequential circuits vulnerable to transient faults violating fundamental mode operations. To overcome non-fundamental mode faults occurring in transient transitions of asynchronous sequential circuits, it is necessary to determine the end of unauthorized state transitions caused by the faults and to stably take the circuit from the faulty state to a desired state that is output equivalent with the normal next stable state. We address the existence condition for a proper output-feedback corrective controller that achieves fault diagnosis and fault-tolerant control for these non-fundamental mode faults. The corrective controller and asynchronous sequential circuit are implemented on field-programming gate array to demonstrate the synthesis procedure and applicability of the proposed control scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1915-1922
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• 2012

In this paper, the Solar Inverter will be monitored by using the AJAX(Asynchronous JavaScript and XML). AJAX is the one of the technologies that can make the RIA(Rich Internet Application) with DHTML(Dynamic Hyper Text Makeup Language) and other java script technology. By using this, a strong application program that is comparable to the general application program can be made. With an existing data-processing technique, the request and response of data can't be processed dynamically on the same page. However, real-time monitoring of data and operation statuses can be confirmed by using the AJAX an asynchronous method of communication. Also without changing the page, the amount of data transmission used the AJAX with significantly small amounts of data to build a Solar Inverter monitoring system that is able to efficiently handle management and monitoring, operating all functions within one page.

• Journal of the HCI Society of Korea
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• v.4 no.1
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• pp.17-27
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• 2009

A computer supported cooperative work(CSCW) system is a collaboration system, which enables cooperative works among various participants through the Internet. A collaborative virtual reality environment(CRVE) can be used in scientific research and cultural research because it can provide users with virtual experiences of three dimensional molecular models in cyberspace. However, general CVRE systems are only focused on synchronous collaborations. We propose a remote collaboration system, which provides synchronous and asynchronous cooperation in collaborative virtual reality environment. The proposed system can be applied to bioscience experiments such as molecular docking process, and crystallography simulation. The proposed system is evaluated in performance comparison with previous approaches.