• Title/Summary/Keyword: Asynchronous Filter

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Development of Underwater Positioning System using Asynchronous Sensors Fusion for Underwater Construction Structures (비동기식 센서 융합을 이용한 수중 구조물 부착형 수중 위치 인식 시스템 개발)

  • Oh, Ji-Youn;Shin, Changjoo;Baek, Seungjae;Jang, In Sung;Jeong, Sang Ki;Seo, Jungmin;Lee, Hwajun;Choi, Jae Ho;Won, Sung Gyu
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.22 no.3
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    • pp.352-361
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    • 2021
  • An underwater positioning method that can be applied to structures for underwater construction is being developed at the Korea Institute of Ocean Science and Technology. The method uses an extended Kalman filter (EKF) based on an inertial navigation system for precise and continuous position estimation. The observation matrix was configured to be variable in order to apply asynchronous measured sensor data in the correction step of the EKF. A Doppler velocity logger (DVL) can acquire signals only when attached to the bottom of an underwater structure, and it is difficult to install and recover. Therefore, a complex sensor device for underwater structure attachment was developed without a DVL in consideration of an underwater construction environment, installation location, system operation convenience, etc.. Its performance was verified through a water tank test. The results are the measured underwater position using an ultra-short baseline, the estimated position using only a position vector, and the estimated position using position/velocity vectors. The results were compared and evaluated using the circular error probability (CEP). As a result, the CEP of the USBL alone was 0.02 m, the CEP of the position estimation with only the position vector corrected was 3.76 m, and the CEP of the position estimation with the position and velocity vectors corrected was 0.06 m. Through this research, it was confirmed that stable underwater positioning can be carried out using asynchronous sensors without a DVL.

Simplified Cubature Kalman Filter for Reducing the Computational Burden and Its Application to the Shipboard INS Transfer Alignment

  • Cho, Seong Yun;Ju, Ho Jin;Park, Chan Gook;Cho, Hyeonjin;Hwang, Junho
    • Journal of Positioning, Navigation, and Timing
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    • v.6 no.4
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    • pp.167-179
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    • 2017
  • In this paper, a simplified Cubature Kalman Filter (SCKF) is proposed to reduce the computation load of CKF, which is then used as a filter for transfer alignment of shipboard INS. CKF is an approximate Bayesian filter that can be applied to non-linear systems. When an initial estimation error is large, convergence characteristic of the CKF is more stable than that of the Extended Kalman Filter (EKF), and the reliability of the filter operation is more ensured than that of the Unscented Kalman Filter (UKF). However, when a system degree is large, the computation amount of CKF is also increased significantly, becoming a burden on real-time implementation in embedded systems. A simplified CKF is proposed to address this problem. This filter is applied to shipboard inertial navigation system (INS) transfer alignment. In the filter design for transfer alignment, measurement type and measurement update rate should be determined first, and if an application target is a ship, lever-arm problem, flexure of the hull, and asynchronous time problem between Master Inertial Navigation System (MINS) and Slave Inertial Navigation System (SINS) should be taken into consideration. In this paper, a transfer alignment filter based on SCKF is designed by considering these problems, and its performance is validated based on simulations.

The Design of Multi-channel Asynchronous Communication IC Using FPGA (FPGA를 이용한 다채널 비동기 통신용 IC 설계)

  • Ock, Seung-Kyu;Yang, Oh
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.1
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    • pp.28-37
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    • 2010
  • In this paper, the IC (Integrated Circuit) for multi-channel asynchronous communication was designed by using FPGA and VHDL language. The existing chips for asynchronous communication that has been used commercially are composed of one to two channels. Therefore, when communication system with two channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 asynchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 256 bytes respectively and consequently high speed communication became possible. To detect errors between communications, it was designed with digital filter and check-sum logic and channel MUX logic so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. It was composed and simulated logic of VHDL described by using Cyclone II Series EP2C35F672C8 and QuartusII V8.1 of ALTERA company. In order to show the performance of designed IC, the test was conducted successfully in QuartusII simulation and experiment and the excellency was compared with TL16C550A of TI (Texas Instrument) company and ATmegal28 general-purpose micro controller of ATMEL company that are used widely as chips for asynchronous communication.

The design of the matched filter for CDMA rapid initial PN code synchronization acquisition using HW reuse scheme (CDMA 고속초기동기획득을 위한 HW 재사용에 의한 정합필터의 설계)

  • Lim, Myoung-Seob
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.11
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    • pp.28-36
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    • 1998
  • In the CDMA mobile communication system with asynchronous mode among base stations, the initial PN code acquisition method using a matched filter can be considered for the rapid PN code synchronization acquisition in the handoff region. In the model of the noncoherent QPSK/DS-SS under the Rayleigh fading channel, the mean acquisttion time of the matched filter is analyzed to have a shortened time in proportion to the length of matched filter to be compared with the serial correlation method. In this paper to improve the HW complexity of the conventional matched device which enables the repeated correlation process, is designed and its function is verified through the FPGAsimulation using Altera MaxPlus Ⅱ.

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The Comparison of Filter Performance in UFMC systems (UFMC 시스템에서 필터성능 비교)

  • Lee, Kyuseop;Choi, Ginkyu
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.17 no.6
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    • pp.89-95
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    • 2017
  • UFMC is known as a candidate for the 5G wireless communication system because it is robust against ICI and better performs in asynchronous situation than OFDM. In the UFMC system, the filtering is performed for each subband so the performance of the filter is very important. The Dolph-Chebyshev filter has been used in conventional UFMC system because of its small out-of-band radiation. However it has distortion in the sub-band and skirt characteristics is not good enough. Therefore, it is necessary to study a new type of UFMC filter which reduces the distortion in the subband and has sharp skirt characteristics. In this paper we analyze the effect of filter frequency response in UFMC system and suggest the wavelet based type of filter that substitutes the Dolph-ChebyShev filter used in the conventional UFMC system. The simulation results show that wavelet filter has better BER performance in multipath fading channels than conventional filters.

Asynchronous Multiuser Receivers with Antenna Arrays in Trellis Coded DS/CDMA Channels (격자부호화 직접수열 부호분할 다중접속 채널에서 안테나 배열을 쓴 비동기 여러쓰는이 수신기)

  • Kim, Kwang-Soon;Lee, Joo-Shik;Kim, Yun-Hee;Park, So-Ryoung;Yoon, Seok-Ho;Song, Iick-Ho
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.36S no.10
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    • pp.10-20
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    • 1999
  • In this paper, we propose and analyze a multiuser receiver using a decorrelating filter and Viterbi decoders for trellis coded DS/CDMA systems with biorthgonal signal constellation in asynchronous channels. The biorthogonality is implemented by user signature waveforms and the decorrelating filter. The performance of the proposed system is investigated with emphasis on the asymptotic cases. It is shown that the proposed system can provide us with some coding gain and near-far resistance. We also analyze the performance of the proposed system with base-station antenna array.

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Design and FPGA Implementation of FBMC Transmitter by using Clock Gating Technique based QAM, Inverse FFT and Filter Bank for Low Power and High Speed Applications

  • Sivakumar, M.;Omkumar, S.
    • Journal of Electrical Engineering and Technology
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    • v.13 no.6
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    • pp.2479-2484
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    • 2018
  • The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

Analysis of the range estimation error of a target in the asynchronous bistatic sonar (비동기 양상태 소나의 표적 거리 추정 오차 분석)

  • Jeong, Euicheol;Kim, Tae-Hwan
    • The Journal of the Acoustical Society of Korea
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    • v.39 no.3
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    • pp.163-169
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    • 2020
  • The asynchronous bistatic sonar needs to estimate direct blast arrival time at a receiver to localize targets, and therefore the direct blast arrival time estimation error could be added to target localization error in comparison with synchronous system. Direct blast especially appears as several peaks at the matched filter output by multipath, thus we compared the first peak detection technique and the maximum peak detection technique of those peaks for direct blast arrival time estimation through sea trial data. The test was performed in a shallow sea with bistatic sonar made up of spatially separated source and line array sensors. Line array sensors obtained the target signal which is generated from the echo repeater. As a result, the first peak detection technique is superior to maximum peak detection technique in direct blast arrival time estimation error. The result of this analysis will be used for further research of target tracking in the asynchronous bistatic sonar.

Design of a Multi-Sensor Data Simulator and Development of Data Fusion Algorithm (다중센서자료 시뮬레이터 설계 및 자료융합 알고리듬 개발)

  • Lee, Yong-Jae;Lee, Ja-Seong;Go, Seon-Jun;Song, Jong-Hwa
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.34 no.5
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    • pp.93-100
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    • 2006
  • This paper presents a multi-sensor data simulator and a data fusion algorithm for tracking high dynamic flight target from Radar and Telemetry System. The designed simulator generates time-asynchronous multiple sensor data with different data rates and communication delays. Measurement noises are incorporated by using realistic sensor models. The proposed fusion algorithm is designed by a 21st order distributed Kalman Filter which is based on the PVA model with sensor bias states. A fault detection and correction logics are included in the algorithm for bad data and sensor faults. The designed algorithm is verified by using both simulation data and actual real data.

Design of Low voltage High speed Phase Locked Loop (고속 저전압 위상 동기 루프(PLL) 설계)

  • Hwang, In-Ho;Cho, Sang-Bock
    • Proceedings of the KIEE Conference
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    • 2007.04a
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    • pp.267-269
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    • 2007
  • PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

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