• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.108-113
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• 2013

This paper describes a low power asynchronous successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for biomedical applications in a 0.35 ${\mu}m$ CMOS technology. The digital-to-analog converter (DAC) uses a capacitive split-arrays consisting of 6-b main array, an attenuation capacitor C and a 5-b sub array for low power consumption and small die area. Moreover, splitting the MSB capacitor into sub-capacitors and an asynchronous SAR reduce power consumption. The measurement results show that the proposed ADC achieved the SNDR of 68.32 dB, the SFDR of 79 dB, and the ENOB (effective number of bits) of 11.05 bits. The measured INL and DNL were 1.9LSB and 1.5LSB, respectively. The power consumption including all the digital circuits is 6.7 ${\mu}W$ at the sampling frequency of 100 KHz under 3.3 V supply voltage and the FoM (figure of merit) is 49 fJ/conversion-step.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.10
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• pp.832-842
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• 2013

Cognitive Radio has attracted intensive interests of the researchers, recently. The data rate always increases in the emerging technologies. The increased data rate poses mainly two challenges for spectrum sensing. One is that the state of primary user (PU) is fast and alternatively varying between "on/off" in a spectrum sensing window. The other is that the asynchronicity among the reports in a cooperative spectrum sensing setting becomes more apparent. Both of them would deteriorate the spectrum sensing performance. Thus, we propose an asynchronous cooperative spectrum sensing method to cope with these two challenges. A likelihood ratio test based spectrum sensing is developed for a single cooperator. The likelihood ratio is obtained in the setting of fast varying PU state. The likelihood ratio test is uniformly powerful according to the Neyman-pearson lemma. Furthermore, the asynchronicity among the cooperators are studied. Two sets of fusion weights are discussed for the asynchronous time among cooperators. One is designed based on the condition probability of the PU state variation and the other one is designed based on the queueing theory. The simulation results are provided with different fusion methods. The performance improvements are demonstrated.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.439-446
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• 2001

The main stream of parallel programming today is using synchronous algorithms, where processor synchronization for correct computation and workload balance are essential. Overall performance of the whole system is dependent upon the performance of the slowest processor, if workload is not well-balanced or heterogeneous clusters are used. Asynchronous iteration is a way to mitigate such problems, but most of the works done so far are for shared memory systems. In this paper, we suggest and implement a parallel large sparse linear system solver that improves performance on distributed memory systems like clusters by reducing processor idle times as much as possible by asynchronous iterations.

• The Journal of Engineering Research
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• v.1 no.1
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• pp.41-48
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• 1997

In this paper, we wxtend DMSA system to support multimedia traffic more efficiently by incorporating a priority scheme. we divide network stations into two types: asynchronous and isosynchronous stations, and we give a priority to the isosynchronous stations over the asynchronous stations by imposing a time-out constraint on the asynchronous stations . we derive the maximum number of isosynchronous stations the proposed priority scheme can support simultaneously and the maximum bandwidth that can be utilized by asynchronous stations in the presence of isosynchronous traffic. We also provide simulation results for the mixed voice and data traffic, and compare them to the analytic results.

• Research in Community and Public Health Nursing
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• v.33 no.3
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• pp.312-320
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• 2022

Purpose: This study was performed to explore the effect of the delivery format on teaching presence, learning presence, and learning outcomes in distance learning of nursing students. Methods: A descriptive survey was conducted to understand teaching presence, learning presence, and learning outcomes depending on the delivery format of distance learning. Quota sampling methodology was used to recruit 295 nursing students from all over the country, and data collection was done from July 27 to September 10, 2020. The first delivery format for distance learning was synchronous learning in which communication between the instructor and students occurred simultaneously. The second delivery format was asynchronous learning in which prerecorded videos were provided and communication did not occur simultaneously. Results: In synchronous learning, teaching presence (especially direct facilitation) and learning presence (especially emotional expression) had a statistical significance that was higher than in asynchronous learning. However, in learning outcomes, there was no statistically significant difference. There were significant positive correlations between teaching presence, learning presence, and learning outcomes, and there were significant positive correlations. Conclusion: It can be suggested that learning outcomes can be improved if presence is improved in the distance learning environment based on the results of this study. It is necessary to add contact with nursing students and instructors to improve teaching presence in the asynchronous learning, and it is necessary to help students express their emotions to improve learning presence.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1380-1386
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• 2011

The request of interrupt accompanies a context switching. If the interrupt is frequently requested, this overhead of context switching can reduce seriously the performance of embedded systems. In order to reduce processing overhead due to frequently requested communication interrupts at Asynchronous Serial Communication, this paper introduces the method of Expanded Asynchronous Serial Communication with the Interrupt Coalescence(IC) that accumulates a fixed number of interrupts and processes them in one time. we implement the existing Asynchronous Serial Communication that requests communication interrupts by one byte at an LN2440SBC embedded board with a uC/OS-II and compare interrupt processing time for the performance evaluation about proposed method. As a result, the communication interrupt processing time of proposed method appears in case of low speed(9,600 bps), the decline of an average 25.18% at transmission, the decline of an average 41.47% at reception. and in case of hight speed(115,200 bps), the decline of an average 16.67% at transmission, the decline of an average 25.61% at reception.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.2
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• pp.86-94
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• 2014

Optical packet switching (OPS) is being considered as one of the switching technologies for a future optical internet. For contention resolution in an optical packet switching (OPS) system, the wavelength dimension is generally used in combination with a fiber delay line (FDL) buffer. In this article, we propose a method to reduce the number of tunable wavelength converters (TWCs) by sharing TWCs for a cost-effective design of an asynchronous OPS system with a shared or an output FDL buffer. Asynchronous and variable-length packets are considered in the OPS system design. To investigate the number of TWCs needed for the OPS system, an algorithm is proposed, which searches for an available TWC and an unused internal wavelength, as well as an outgoing channel. This algorithm is applied to an OPS system with a shared or an output FDL buffer. Also, the number of internal wavelengths (i.e., the conversion range of the TWC) needed for an asynchronous OPS system is presented for cost reduction of the OPS system.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.17-25
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• 2016

This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.