• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.219-224
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• 2015

Recently, the multi-core processor architecture is widely used in the digital signal processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multi-core processors are known to have higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core digital signal processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric quad-core, octa-core and hexadeca-core digital signal processors and compared with the symmetric ones of similar hardware budget using UTDSP benchmarks as input.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.233-238
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• 2016

Recently, the multi-core processor architecture is widely adopted in the embedded processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multicore processors are known to score higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core embedded processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric embedded dual-core, quad-core, octa-core and hexadeca-core processors and compared with the symmetric ones of similar hardware budget using MiBench benchmarks as input.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.157-163
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• 2016

If trace-driven or execution-driven simulation is used for the performance analysis of asymmetric multi-core processors, excessive time and much disk space are necessary. In this paper, statistical simulations are performed for asymmetric multi-core processors with various hardware configurations. For the experiment, SPEC 2000 benchmark programs are used for profiling and synthesis, which is supplied as input for the simulation of asymmetric multi-core processors. As a result, the performance of asymmetric multi-core processor obtained by statistical simulation is comparable to that of the trace-driven simulation with a tremendous reduction in the simulation time.

• Journal of Korea Society of Industrial Information Systems
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• v.26 no.5
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• pp.11-19
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• 2021

In this paper, we proposed an asymmetric multi-core processor scheduling scheme which is based on the mileage of each core. We considered a big-LITTLE multi-core processor structure, which consists of low power consuming LITTLE cores with general performance and high power consuming big cores with high performance. If a task needs to be processed, the processor decides a core type (big or LITTLE) to handle the task, and then investigate the core with the shortest mileage among unoccupied cores. Then assigns the task to the core. We developed a mileage-based balancing algorithm for asymmetric multi-core assignment and showed that the proposed scheduling scheme is more cost-effective compared to the traditional scheme from a management perspective. Simulation is also conducted for the purpose of performance evaluation of our proposed algorithm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.163-169
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• 2014

Recently, the importance of multicore processor system is growing rapidly. Multicore processors are classified either as symmetric or asymmetric. Asymmetric multicore processors consist of a high performance complex core and number of low performance simple cores, and are known to be more efficient than symmetric multicore processors. Therefore, performance impact on various configurations of asymmetric multi-core processor needs to be studied. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for different asymmetric quad-core and octa-core processors and compared to the corresponding symmetric ones.

• Journal of IKEEE
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• v.19 no.3
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• pp.357-365
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• 2015

Recently, embedded systems such as aircraft and automobilie, are developed as modular architecture instead of federated architecture because of SWaP(Size, Weight and Power) issues. In addition, partition operating system that support multiple logical node based on partition concept were recently appeared. Distributed recovery block is fault tolerance design scheme that applicable to mission critical real-time system to support real-time take over via real-time synchronization between participated nodes. Because of real-time synchronization, single-core based computer is not suitable for partition based distributed recovery block design scheme. Multi-core and AMP(Asymmetric Multi-Processing) based partition architecture is required to apply distributed recovery block design scheme. In this paper, we proposed design scheme of distributed recovery block on the multi-core based supervised-AMP architecture partition operating system. This paper implements flight control simulator for avionics to check feasibility of our design scheme.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.4
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• pp.113-120
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• 2014

In this paper, we examine Asymmetric Multi-Processing Environment to provide LDW service. Asymmetric Multi-Processing Environment consists of high-speed MCU to support rapid image processing and low-speed MCU for controlling with other ECU at the control domain. Also we designed rapid image process application and LDW application Software Component(SW-C) according to the development process rule of AUTOSAR. To communicate between two MCUs, timer based polling based IPC was designed. Also to communicate with other ECUs(Electronic Control Units), we designed CAN messages to provide alarm information and receiving CAN message to catch the Turn signal. We confirm the possibility of the various ADAS development using an Asymmetric Multi-Processing Environment and AUTOSAR platform. We also expect providing ISO 26262 functional safety.

• Journal of Aerospace System Engineering
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• v.13 no.5
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• pp.1-8
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• 2019

Recently, avionics has been migrating from a federated architecture to an integrated modular architecture based on a multi-core to reduce the number of systems, weight, power consumption, and platform redundancy. The volume of data which must bo provided to the pilot through the display device has increased, because an integrated single device performs multiple functions. For this reason, the volume of data processed by the graphic processor within a fixed operation period has increased. In this paper, we provide a multi-core-based rendering engine in to perform more graphics processing within a fixed operation period. We assume the proposed method uses a multi-core-based partitioning operating system using the AMP (Asymmetric Multi-Processing) architecture.

• Nuclear Engineering and Technology
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• v.55 no.5
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• pp.1651-1664
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• 2023

It is very difficult to capture the multi-dimensional phenomena such as asymmetric flow and temperature distributions with the one-dimensional (1D) model, obviously, due to its inherent limitation. In order to overcome such a limitation of the 1D representation, many state-of-the-art system codes have equipped a three-dimensional (3D) component for multi-dimensional analysis capability. In this study, a standard multi-dimensional analysis model of APR1400 (Advanced Power Reactor 1400) has been developed using TRACE (TRAC/RELAP Advanced Computational Engine). The entire reactor pressure vessel (RPV) of APR1400 has been modeled using a single 3D component. The fuels in the reactor core have been described with detailed and coarse representations, respectively, to figure out the impact of the fuel description. Using both 3D RPV models, a comparative analysis has been performed postulating a double-ended guillotine break at a cold leg. Based on the results of comparative analysis, it is revealed that both models show no significant difference in general plant behavior and the model with coarse fuel model could be used for faster transient analysis without reactor kinetics coupling. The analysis indicates that the asymmetric temperature and flow distributions are captured during the transient, and such nonuniform distributions contribute to asymmetric quenching behaviors during blowdown and reflood phases. Such asymmetries are directly connected to the figure of merits in the LBLOCA analysis. Therefore, it is recommended to employ a multi-dimensional RPV model with a detailed fuel description for a realistic safety analysis with the consideration of the spatial configuration of the reactor core.

• Journal of the Korean Society for Precision Engineering
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• v.25 no.12
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• pp.39-46
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• 2008

Asymmetric glass lens core for portable projection optic system was designed and simulated. And it was machined by newly developed non-rotational ultra precision grinding method. With the designed lens data which optimized for multi-collimation, we generated the we core surface data. Mold pressing conditions analyzed by FEM. In the machining process, ground profile errors were compensated based on measured data, minimized feed rate and depth of cut. The deviations of machined core profile were acceptable level for glass mold press. Mold pressed glass array lens was coated with $SiO_2\;and\;Ta_2O_5$ for anti-reflection.