• ETRI Journal
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• 제35권3호
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• pp.378-385
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• 2013

An S-band multifunction chip with a simple interface for an active phased array base station antenna for next-generation mobile communications is designed and fabricated using commercial 0.5-${\mu}m$ GaAs pHEMT technology. To reduce the cost of the module assembly and to reduce the number of chip interfaces for a compact transmit/receive module, a digital serial-to-parallel converter and an active bias circuit are integrated into the designed chip. The chip can be controlled and driven using only five interfaces. With 6-bit phase shifting and 6-bit attenuation, it provides a wideband performance employing a shunt-feedback technique for amplifiers. With a compact size of 16 $mm^2$ ($4mm{\times}4mm$), the proposed chip exhibits a gain of 26 dB, a P1dB of 12 dBm, and a noise figure of 3.5 dB over a wide frequency range of 1.8 GHz to 3.2 GHz.

• 전자공학회논문지B
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• 제33B권2호
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• 전자공학회논문지C
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• 제35C권2호
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• 한국전기전자재료학회논문지
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• 제17권7호
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• pp.729-737
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• 2004

In this paper, a DNA chip with a microelectrode array was fabricated using microfabrication technology. Several probe DNAs consisting of mercaptohexyl moiety at their 5 end were immobilized on the gold electrodes by DNA arrayer. Then target DNAs were hybridized and reacted with Hoechst 33258, which is a DNA minor groove binder and electrochemically active dye. Linear sweep voltammetry or cyclic voltammetry showed a difference between target DNA and control DNA in the anodic peak current values. It was derived from Hoechst 33258 concentrated at the electrode surface through association with formed hybrid. It suggested that this DNA chip could recognize the sequence specific genes.

• Molecules and Cells
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• 제45권2호
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• pp.76-83
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• 2022

Neurons-on-a-Chip technology has been developed to provide diverse in vitro neuro-tools to study neuritogenesis, synaptogensis, axon guidance, and network dynamics. The two core enabling technologies are soft-lithography and microelectrode array technology. Soft lithography technology made it possible to fabricate microstamps and microfluidic channel devices with a simple replica molding method in a biological laboratory and innovatively reduced the turn-around time from assay design to chip fabrication, facilitating various experimental designs. To control nerve cell behaviors at the single cell level via chemical cues, surface biofunctionalization methods and micropatterning techniques were developed. Microelectrode chip technology, which provides a functional readout by measuring the electrophysiological signals from individual neurons, has become a popular platform to investigate neural information processing in networks. Due to these key advances, it is possible to study the relationship between the network structure and functions, and they have opened a new era of neurobiology and will become standard tools in the near future.

• ETRI Journal
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• 제27권5호
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• pp.585-594
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• 2005

A small electronic nose (E-Nose) system has been developed using an 8-channel vapor detection array and personal digital assistant (PDA). The sensor array chip, integrated on a single microheater-embedded polyimide substrate, was made of carbon black-polymer composites with different kinds of polymers and plasticizers. We have successfully classified various volatile organic compounds such as methanol, ethanol, i-propanol, benzene, toluene, n-hexane, n-heptane, and c-hexane with the aid of the sensor array chip, and have evaluated the resolution factors among them, quantitatively. To achieve a PDA-based E-Nose system, we have also elaborated small sensor-interrogating circuits, simple vapor delivery components, and data acquisition and processing programs. As preliminary results show, the miniaturized E-Nose system has demonstrated the identification of essential oils extracted from mint, lavender, and eucalyptus plants.

• Journal of Electrical Engineering and information Science
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• 제2권4호
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• pp.8-13
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• 1997

This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicated in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. it has the initial latency of N+3 cycles with NxN array configuration. We designed an experimental 200 MHz 4Kb static RAM chip with the 4x4 array configuration of 256 SRAM blocks. It was fabricated is 0.8$\mu\textrm{m}$ twin-well single-poly double-metal CMOS technology.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.426-427
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• 2005

This research describes a new constructing method of multifunctional biosensor using many kinds of biomaterials. A metal particle and an array was fabricated by photolithographic. Biomaterials were immobilized on the metal particle. The array and the particles were mixed in a buffer solution, and were arranged by magnetic force interaction and self-assembly. A quarter of total Ni dots were covered by the particles. The binding direction of the particles was controllable, and condition of particles was almost with Au surface on top. The particles were successfully arranged on the array. The biomaterial activities were detected by chemiluminescence and electrochemical methods.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 1998년도 가을 학술발표논문집 Vol.25 No.2 (3)
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• pp.691-693
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• 1998

A parallel processing systolic array reduces execution time of the Back-propagation ANN. But, systolic array must be designed whenever the number of neurons in the ANN differ. To use the systolic array which is aready designed ad a fixed size VLSI chip, partition of the problem size systolic array must be performed. This paper presents a design method of the fixed size systolic array for the Back-propagation algorthm using LSGP and LPGS partion method

• 한국재료학회:학술대회논문집
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• 한국재료학회 2007년도 추계학술발표대회 및
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• pp.3.1-3.1
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• 2007