• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1207-1212
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• 2013

Arithmetic operations over finite fields are widely used in coding theory and cryptography. In both of these applications, there is a need to design low complexity finite field arithmetic units. The complexity of such a unit largely depends on how the field elements are represented. Among them, representation of elements using a optimal normal basis is quite attractive. Using an algorithm minimizing the number of 1's of multiplication matrix, in this paper, we propose a multiplier which is time and area efficient over finite fields with optimal normal basis.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.910-920
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• 1990

This paper presents a method of constructing an Arithmetic Operation Unit Systems (A.O.U.S.) over Galois Field GF(2**m) for the purpose of the four arithmetical operation(addition, subtraction, multiplication and division between two elements in GF(2**mm). The proposed A.O.U.S. is constructed by following procedure. First of all, we obtained each four arithmetical operation algorithms for performing the four arithmetical operations using by mathematical properties over GF(2**m). Next, for the purpose of realizing the four arithmetical unit module (adder module, subtracter module, multiplier module and divider module), we constructed basic cells using the four arithmetical operation algorithms. Then, we realized the four Arithmetical Operation Unit Modules(A.O.U.M.) using basic cells and we constructd distributor modules for the purpose of merging A.O.U.M. with distributor modules. Finally, we constructed the A.O.U.S. over GF(2**m) by synthesizing A.O.U.M. with distributor modules. We prospect that we are able to construct an Arithmetic & Logical Operation Unit Systems (A.L.O.U.S.) if we will merge the proposed A.O.U.S. in this paper with Logical Operation Unit Systems (L.O.U.S.).

• Progress in Superconductivity
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• v.6 no.2
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• Progress in Superconductivity
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• v.7 no.2
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• The KIPS Transactions:PartC
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• v.9C no.2
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• pp.163-172
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• 2002

Java Card API porvide benifit for development program based on smart card using limmited resource. This APIs does not support arithmetic operations such as modular arithmetic, greatest common divisor calculation, and generation and certification of prime number, which is necessary arithmetic in PKI algorithm implementation. In this paper, we implement class BigInteger acted in the Java Card platform because that Java Card APIs does not support class BigInteger necessary in implementation of PKI algorithm.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1113-1116
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• 1998

This paper presents an efficient hardware architecture of demodulating fingers to demodulate the multi-path propagating signals in MC-CDMA Mobile System. We design a new architecture of demodulating fingers which share the single arithmetic unit to reduce the hardware complexity. This arithmetic unit performs MAC(Multiplication and Accumulation) operations of all demodulating fingers. The proposed architecture is suitable for Is-95 based CDMA PCS system. Three demodulating fingers for MC-CDMA which demodulate 7 channels contain about 42K logic gates. Our proposed system is shown to be very useful for Multi-Code CDMA system in which several channels are demodulated simultaneously.

• Progress in Superconductivity
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• v.5 no.1
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• pp.21-25
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• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.7
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• pp.520-534
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• 1991

This paper describes the design of an ALU and a shifter for RISC. The RISC datapath is designed to have a 4-stage pipeline and a 20 MHz operating frequency. The ALU makes use of the 32-bit BLC adder which has the characteristics of high speed ane regular structuer and executes the arithmetic instructions-addition and subtraction- and the logical instructions-AND, OR, and XOR. Additionally, multiplication is possible by iterative executions of step instructions to perform shift and add operations. The shifter is implemented by using the modified of funnel shifter. The shifter is able to perform the arithmetic andlogical shift instructions without maskiog. Moreover, it carries out data align operation which conforms to big endian byte address. The logical operation of the desinged ALU and the shifter were simulated using YSLOG and VLSIsim. SPICE simulation results using 1.2um double metal process parameters show that the ALU and shifter have a delay time of 15.9NS and 9.9NS, respectively. Therefore, the ALU and the shifter operates correctly above 20[ MHz ] click ferquency and are composed of about 7K and 15K teansistors, respectively.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.27-33
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• 1993

This paper describes the hardware implementation of 2-D FIR digital filter for a real-time image processing. Generally, the most time-consuming operation in signal processing is the multiplication operation. To avoid it in digital filter. Pelid and Liu proposed the distributed arithmetic method for the one-dimensional case. The implementation method proposed in this paper is to extend Pelid's method to two-dimensional FIR filter using simple ROM lookup table and to use the technique of pipe lining two main operations of memory access and arithmetic. As a result, the speed of our proposed hardware implementation is two times faster than that of conventional methods and can be close to the real time speed.