• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1471-1479
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• 2017

This paper describes a design of RSA public-key cryptography processor supporting key length of 2,048 bits. A modular multiplier that is core arithmetic function in RSA cryptography was designed using word-based Montgomery multiplication algorithm, and a modular exponentiation was implemented by using Left-to-Right (LR) binary exponentiation algorithm. A computation of a modular multiplication takes 8,386 clock cycles, and RSA encryption and decryption requires 185,724 and 25,561,076 clock cycles, respectively. The RSA processor was verified by FPGA implementation using Virtex5 device. The RSA cryptographic processor synthesized with 100 MHz clock frequency using a 0.18 um CMOS cell library occupies 12,540 gate equivalents (GEs) and 12 kbits memory. It was estimated that the RSA processor can operate up to 165 MHz, and the estimated time for RSA encryption and decryption operations are 1.12 ms and 154.91 ms, respectively.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.4
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• pp.143-150
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• 2013

The School Curriculum amend in 2007 mandates the contents from which students can learn the principles and concepts of computer science. Computer Science is one of the most rapidly changing subjects, and the Informatics textbook should accurately explain the basic principles and concepts based on the latest technology. However, we found that the middle school textbooks in circulation lack accuracy and consistency in describing CPU. This paper attempted to discover the root-cause of the fallacy and suggest timely and appropriate explanation based on the historical and technical analysis. According to our study, it is appropriate to state that CPU is composed of datapath and control unit. The Datapath performs operations on data and holds data temporarily, and it is composed of the hardware components such as memory, register, ALU and adder. The Control unit decides the operation types of datapath elements, main memory and I/O devices. Nevertheless, considering the technological literacy of middle school students, we suggest the terms, 'arithmetic part' and 'control part' instead of datapath and control unit.

• Journal of Korea Water Resources Association
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• v.41 no.10
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• pp.1059-1065
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• 2008

Rainfall data is the most basic input data to analyze the hydrological phenomena and can be missing due to various reasons. In this research, a neural network based model to estimate missing rainfall data as approximate values was developed for 12 rainfall stations in the Soyang river basin to improve existing methods. This approach using neural network has shown to be useful in many applications to deal with complicated natural phenomena and displayed better results compared to the popular offline estimating methods, such as RDS(Reciprocal Distance Squared) method and AMM(Arithmetic Mean Method). Additionally, we proposed automated data reconciliation systems composed of a neural network learning processer to be capable of real-time reconciliation to transmit reliable hydrological data online.

• Journal of Advanced Navigation Technology
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• v.8 no.2
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• pp.190-196
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• 2004

The development of a new hardware structure which can implement the viterbi algorithm efficiently is required for applications such as a software radio because the viterbi algorithm, which is an error correction code function for the second and the third generation of mobile communication, needs a lot of arithmetic operations. The length of K in the viterbi algorithm different from each standard, for examples, K=7 in case of IS-95 standard and GSM standard, and K=9 in case of WCDMA and CDMA2000. In this paper, we propose a new hardware structure of an adaptive viterbi decoder which can decode the constraint length in K=3~9 and the data rate in 1/2 ~ 1/3. Prototyping results targeted to Altera Cyclon EPIC20F400C8, shows that the proposed hardware structure needs maximum 19,276 logic elements and power dissipation of 222.6 mW.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.1 no.1
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• pp.23-35
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• 1983

In its global meaning language translation refers to the process whereby a program which is executable in one computer can be executed in another computer directly to obtain the same result. There are four different ways of approaching translation. The first way is translation by a Translator or a Compier, the second way is Interpretation, the third way is Simulation, the last way is Emulation. This paper introduces the M-C Translator which was designed as the first way of translation. The MUSS 80 language (the subsystem of the UNIVAC Solid State 80 S-4 assembly language system) was chosen as the source language which includes forty-three instructions, using the CYBER COMPASS as the object language. The M-C translator is a two pass translator and is a two pas translator and es written in Fortran Extended language. For this M-C Translation, seven COMPASS subroutines and a set of thirty-five macros were prepared. Each executable source instruction corresponds to a macro, so it will be a macro instruction within the object profram. Subroutines are used to retain and handle the source data representation the same way in the object program as in the source system, and are used to convert the decimal source data into the equivalent binary result into the equivalent USS-80digits before and after arithmetic operations. The source instructions can be classified into three categories. First, therd are some instructions which are meaningless in the object system and are therefore unnecessary to translate, and the remaining instructions should be translated. Second, There are some instructions are required to indicate dual address portions. Third, there are Three instructions which have overflow conditions, which are lacking in the remaining instructions. The construction and functions of the M-C Translator, are explained including some of the subroutines, and macros. The problems, difficulties and the method of solving them, and easier features on this translation are analysed. The study of how to save memory and time will be continued.

• The KIPS Transactions:PartC
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• v.17C no.2
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• pp.145-152
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• 2010

In this paper, we first propose a fast division algorithm in GF($2^{163}$) using standard basis representation, and then it is mapped into divider for GF($2^{163}$) with iterative hardware structure. The proposed algorithm is based on the binary ExtendedGCD algorithm, and the arithmetic operations for modular reduction are performed within only one "while-statement" unlike conventional approach which uses two "while-statement". In this paper, we use reduction polynomial $f(x)=x^{163}+x^7+x^6+x^3+1$ that is recommended in SEC2(Standards for Efficient Cryptography) using standard basis representation, where degree m = 163. We also have implemented the proposed iterative architecture in FPGA using Verilog HDL, and it operates at a clock frequency of 85 MHz on Xilinx-VirtexII XC2V8000 FPGA device. From implementation results, we will show that computation speed of the proposed scheme is significantly improved than the existing two approaches.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.6
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• pp.1104-1114
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• 2007

Digital video compression technique has played an important role that enables efficient transmission and storage of multimedia data where bandwidth and storage space are limited. The new video coding standard, H.264/AVC, developed by Joint Video Team(JVT) significantly outperforms previous standards in compression performance. Especially, variable length code(VLC) plays a crucial pun in video and image compression applications. H.264/AVC standard adopted Context-based Adaptive Variable Length Coding(CAVLC) as the entropy coding method. CAVLC of H.264/AVC requires a large number of the memory accesses. This is a serious problem for applications such as DMB and video phone service because of the considerable amount of power that is consumed in accessing the memory. In order to overcome this problem in this paper, we propose a variable length technique that implements memory-free coeff_token, level, and run_before decoding based on arithmetic operations and using only 70% of the required memory at total_zero variable length decoding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2031-2038
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• 2008

A small-area and high-speed authentication/security processor (WUSB_Sec) IP is designed, which performs the 4-way handshake protocol for authentication between host and device, and data encryption/decryption of wireless USB system. The PRF-256 and PRF-64 are implemented by CCM (Counter mode with CBC-MAC) operation, and the CCM is designed with two AES (Advanced Encryption Standard) encryption coles working concurrently for parallel processing of CBC mode and CTR mode operations. The AES core that is an essential block of the WUSB_Sec processor is designed by applying composite field arithmetic on AF$(((2^2)^2)^2)$. Also, S-Box sharing between SubByte block and key scheduler block reduces the gate count by 10%. The designed WUSB_Sec processor has 25,000 gates and the estimated throughput rate is about 480Mbps at 120MHz clock frequency.

• Journal of Convergence for Information Technology
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• v.11 no.10
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• pp.10-19
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• 2021

In this paper, we tried to derive characteristic parameters that reflect mental fatigue through EEG measurement and analysis. For this purpose, mental fatigue was induced through a resting state with eyes closed and performing subtraction operations in mental arithmetic for 30 minutes. Five subjects participated in the experiment, and all subjects were right-handed male students in university, with an average age of 25.5 years. Spectral analysis was performed on the EEG collected at the beginning and the end of the experiment to derive feature parameters reflecting mental fatigue. As a result of the analysis, the absolute power of the alpha band in the occipital lobe and the temporal lobe increased as the mental fatigue increased, while the relative power decreased. Also, the difference in power between resting state and task state showed that the relative power was larger than the absolute power. These results indicate that alpha relative power in the occipital lobe and temporal lobe is a feature parameter reflecting mental fatigue. The results of this study can be utilized as feature parameters for the development of an automated system for mental fatigue determination such as fatigue and drowsiness while driving.

• The Journal of the Korea Contents Association
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• v.21 no.9
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• pp.42-50
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• 2021

As the Internet environment develops, data-analysis-based applications have been widely and extensively used in the past decade. However, these applications potentially have a privacy problem in that users' personal information may be leaked to unauthorized parties. To tackle such a problem, researchers have suggested several techniques including data perturbation and cryptography. The homomorphic encryption algorithm is a relatively new cryptography technology that allows arithmetic operations for encrypted values as it is without decryption. Since original values are not required, we believe that this method provides better privacy protection than other existing solutions. In this work, we propose to apply a homomorphic encryption algorithm that protects personal information while enabling data analysis.