• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1644-1649
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• 2019

With the rapid development of mobile communication systems, various mobile convergence services are appearing and data traffic is exploding accordingly. Because the number of base stations to support these surging devices is also increasing, from a network provider's point of view, reducing energy consumption through these mobile communication networks is one of the most important issues. Therefore, in this paper, we apply the DBSCAN (density-based spatial clustering of applications with noise) algorithm, one of the representative user-density based clustering algorithms, in order to extract the dense area with user density and apply the thinning process to each extracted sub-network to efficiently control the mode of the base stations. Extensive simulations show that the proposed algorithm has better performance results than the conventional algorithms with respect to area throughput and energy efficiency.

• Journal of Korea Multimedia Society
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• v.14 no.10
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• pp.1275-1286
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• 2011

This paper proposes a high speed systolic array architecture for full search block matching algorithm (FBMA). The pixels of the search area for a reference block are input only one time to find the matched candidate block and reused to compute the sum of absolute difference (SAD) for the adjacent candidate blocks. Each row of designed 2-dimensional systolic array compares the reference block with the adjacent blocks of the same row in search area. The lower rows of the designed array get the pixels from the upper row and compute the SAD with reusing the overlapped pixels of the candidate blocks within same column of the search area. This designed array has no data broadcasting and global paths. The comparison with existing architectures shows that this array is superior in terms of throughput through it requires a little more hardware.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.1184-1201
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• 1995

Two multiple access protocols are proposed for a multichannel WDM optical fibre local area network or metropolitan area network in which users are interconnected using a passive star topology. Each user has a single tunable transmitter and a single tunable receiver. A transmitter sends a control packet before its data packet transmission so that its intended receivers can tune to the proper data channel wavelength. The maximum throughput of the proposed protocols are independent of the effective normalized propagation delay which may include the transmitter and receiver tuning times and the processing delays. The maximum throughputs of the protocols are analyzed and compared with those of the existing ones by numerical examples. The message delay of the R- Aloha/synchronous N-server switch protocol which is suitable for the queued users is also analyzed.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2011.06a
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• pp.234-236
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• 2011

Saigon Port within the port system of the Vietnam Maritime sector is one of the port having highest throughput and productivity in the country. The marine traffic of Saigon water ways is the heaviest in Vietnam and the number of marine accidents in this area are much higher than the others area in Vietnam. In order to reduce the risk of the accident in Saigon fairway, this paper concentrates on marine accident frequency in this area. The marine traffic and the marine accident were analyzed to find out the probability of vessel collision and the marine traffic risk. It follows that the main shipping route through Saigon fairway has the high risk of ship-ship collision.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.6
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• pp.632-638
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• 1997

The growing number of electronic components used in automobiles has given rise to problems concerning the increasing number, size and weight of the wiring harnesses. As an approach to resolve these problems, multiplexed wiring systems using automotive communication protocol such as Controller Area Network(CAN), Advanced PALMNET and J1850 have been developed by many automobile companies. In order to compare these protocols quantitatively, this paper presents the performance evaluation of CAN and Advanced PALMNET via discrete event simulation. Through numerous simulation experiments, several important quantitative performance factors such as the probability of a transmission failure, average system delay(data latency), and throughput have been evaluated.

• ETRI Journal
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• v.41 no.4
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• pp.452-464
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• 2019

The use of wireless body area networks (WBANs) in healthcare applications has made it convenient to monitor both health personnel and patient status continuously in real time through wearable wireless sensor nodes. However, the heterogeneous and complex network structure of WBANs has some disadvantages in terms of control and management. The software-defined network (SDN) approach is a promising technology that defines a new design and management approach for network communications. In order to create more flexible and dynamic network structures in WBANs, this study uses the SDN approach. For this, a WBAN architecture based on the SDN approach with a new energy-aware routing algorithm for healthcare architecture is proposed. To develop a more flexible architecture, a controller that manages all HUBs is designed. The proposed architecture is modeled using the Riverbed Modeler software for performance analysis. The simulation results show that the SDN-based structure meets the service quality requirements and shows superior performance in terms of energy consumption, throughput, successful transmission rate, and delay parameters according to the traditional routing approach.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.53-59
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• 2011

Recently there have been considerable attentions on nanoimprint lithography (NIL) by the display device and semiconductor industry due to its potential abilities that enable cost-effective and high-throughput nanofabrication. Although one of the current major research trends of NIL is large-area patterning, the technical difficulties to keep the uniformity of the residual layer become severer as the imprinting area increases more and more. In this paper we focused on the deformation of the $2^{nd}$ generation TFT-LCD sized ($370{\times}470mm^2$) large-area soft mold in the UV imprinting process. A mold was fabricated with PDMS(Poly-dimethyl Siloxane) layered glass back plate(t0.5). Besides, the mold includes large surrounding wall type protrusions of 1.9 mm width and the via-hole(7 ${\mu}m$ diameter) patterend area. The large surrounding wall type protrusions cause the proximity effect which severely degrades the uniformity of residual layer in the via-hole patterend area. Therefore the deformation of the mold was calculated by finite element analysis to assess the effect of large surrounding wall type protrusions and the flexiblity of the mold. The deformation of soft mold was verified by the measurements qualitatively.

• Journal of Broadcast Engineering
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• v.20 no.2
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• pp.300-309
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• 2015

In IEEE 802.11n WLANs(Wireless Local Area Networks), to support high throughput, MAC(Media Access Control) layer adopts A-MSDU(Aggregate-MAC Service Data Unit) and A-MPDU(Aggregate-MAC Protocol Data Unit). Generally, as the A-MPDU uses a selective retransmission capability, A-MPDU provides higher throughput than A-MSDU. However, although A-MPDU uses the selective re-transmission capability, if the size of MPDU within A-MPDU is smaller than the size of minimum MPDU starting spacing, A-MPDU can reduce throughput because of the overhead of retransmission owing to the addition of delimiter, that is a dummy MPDU. Therefore, to overcome the above problem, two-level Aggregation method, where the small MPDU within A-MPDU is replaced by not delimiter but A-MSDU, has been introduced. In the two-level Aggregation method, the existing re-transmission scheme retransmits only A-MPDU, but if the size of retransmission data is smaller than the size of the minimum MPDU starting spacing, the proposed retransmission scheme retransmits the aggregated retransmission data and MSDUs. Therefore, we know that the proposed retransmission scheme have better throughput that the existing retransmission scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.22-30
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• 2011

In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered $0.18{\mu}m$ CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.