• 제목/요약/키워드: Architecture Minimize

검색결과 508건 처리시간 0.024초

에코센터의 생태건축기술에 관한 연구 - 건축재료와 태양에너지활용시스템을 중심으로 - (A Study on the Eco-Tecnique of EcoCenter - Focused on the Building Material and Solar System -)

  • 최영호;심우갑
    • KIEAE Journal
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    • 제4권2호
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    • pp.65-72
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    • 2004
  • Ecological architecture enables people to recycle and reuse architectural resources within the category of ecosystem and also to minimize the effect on environment in a whole process, including architectural planning, usage and exhaustion to use sustainable energies. Rammed earth wall construction method utilized in EcoCenter located in Crystalwaters ecological village in Austrailia is a good example, which maximizes its advantages and also covers its limits to use soil and wood as structural resources. In a case of wood, they used non-treated timber to minimize environmental load and utilized used materials in openings. In the roofs, aluminum coated steel which is plated with zinc collects rain effectively even though it is not regenerable. Nontoxic finishes and insulation in floor and ceiling with used papers are able to minimize its environmental load. Solar energy system applied in EcoCenter enables them to market extra energy with electricity companies as well as support needs of its own buildings to utilize photovoltaic panel system with PV panels. Passive solar system is planned effectively in heating and cooling to apply regenerative walls in a use of rammed earth wall construction and natural ventilation systems through openings.

결함허용 실시간 시스템 구조에 대한 설계 및 구현 (Design and Implementation of a Architecture For Fault-Tolerant and Real-Time System)

  • 유종상;김범식;신인철
    • 한국산업정보학회:학술대회논문집
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    • 한국산업정보학회 1997년도 추계학술대회 발표논문집:21세기를 향한 정보통신 기술의 전망
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    • pp.417-433
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    • 1997
  • A real-time operating system has focused primary on techniques to minimize processing time, with a secondary emphasis on system reliability issues. Conversely, fault-tolerant system has concentrated on using recourse and information redundancy to maximize the availability and reliability of the system, with a lesser emphasis on performance. We have developed a fault-tolerant and real-time operations system which support a powerful concurrent runtime environment under the above requirements. In this paper, we present an overview of real-time systems, design and implementation of a duplex architecture using advanced concepts and technologies such as fast " fault detection", "fault isolation" and "fault recovery" Because the duplex architecture has two dentical hardware elements and has several recovery steps and hierarchy to facilitate a fast recovery which must be proceeded by a prompt fault detection and isolation. Thus it makes possible to minimize the overhead of the systems including hardware and software and guarantee the service continuity of he systems.

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영상의 깜박거림 현상을 최소화하기 위한 순환 루프 필터의 설계 (Design of IIR Loop Filter to minimize A flick Phenomenon of An image)

  • O. Moon;Lee, B.;Lee, H.;Lee, Y.;B. Kang;C. Hong
    • 융합신호처리학회 학술대회논문집
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    • 한국신호처리시스템학회 2000년도 추계종합학술대회논문집
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    • pp.165-168
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    • 2000
  • In this paper, we propose a method, an optimized architecture of a device with an image signal process of a field unit to minimize the flick phenomenon that happens in direction of a color temperature at a color tone change. The proposed IIR loop filter has an optimized architecture and reduced hardware compared with previous filters. In order to achieve the optimization for the hardware complexity. It is designed by time-multiplexing architecture. The proposed IIR loop filter is synthesized by using the STD90 0.35um cell library.

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조경공사의 설계와 시공일치를 위한 최적 모형 (An Optimization Model for Concurring Landscape Detailed Design with Final Products)

  • 이용훈;이기의;서옥하
    • 한국조경학회지
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    • 제28권4호
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    • pp.105-116
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    • 2000
  • The purpose of this paper is to minimize differences between landscape detailed design (hereafter 'design') and final landscape construction products in working sites (hereafter 'products'). Ten landscape sites constructed in recent two years were selected to examine the differences. Differences in quantities and quality between design and products were surveyed and the results were analyzed with the 'differential analysis method'. The method employed in this paper can be used as an optimization model to minimize the differences between design and products. This paper suggests that every landscape field should mark less than 13.672% calculated from the 10% of total amount for excellent construction products. This should be approved by the president, according to the Clause 20 of General Conditions of the Contract, divided by the ratio of quantities affecting mainly he average Difference in Value between Design and Construction(DVDC). This value can be the critical point from the differential analysis method for the optimal maximum DVDC between landscape design and final landscape construction products in fields.

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A STUDY ON SPACE ZONING BY COMPUTING IDLE-TIMES IN CONSTRUCTION PROCESSES

  • Sang-Min Park;Won-Suk Jang;Dong-Eun Lee
    • 국제학술발표논문집
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    • The 5th International Conference on Construction Engineering and Project Management
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    • pp.509-512
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    • 2013
  • An inappropriate space zoning plan causes the unnecessary transportation of construction material and equipment among work areas and increases the disorder of work space. Space zoning is an essential operation management technique which contributes to reduce the process and/or operation idle-time. This paper introduces a method that computes the idle-times between construction operations (or processes) by using Web-CYCLONE. It allows computing with idle-times that affect the construction productivity. Using the idle time between operations and between processes, it computes the optimal number of zones and finds the optimal combination of zones that minimize the idle times. The method contributes to minimize the idle times relative to the operation schedule using complete enumeration. This paper presents the system prototype in detail. A case study is presented to demonstrate the system and verifies the validity of the model. It allows a project manager to establish space zoning plan that effectively segregates a project into optimal number of construction zones and to assign the constrained resources (e.g., laborer, equipment).

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적응 제어 기반 Portable 용접 로봇 시뮬레이터 개발 (Development of a Motion Simulator for Portable Type Welding Robot Based on Adaptive Control)

  • 구남국;하솔;노명일
    • 대한조선학회논문집
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    • 제49권5호
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    • pp.400-409
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    • 2012
  • It is not easy to know the accurate mass and mass moment of inertia of robot. Because of this uncertainty, error may exist when we control the robot based on the inaccurate mass information. Moreover the properties of the portable robot can change during its operation. Therefore we developed the motion simulator based on the adaptive control. First, the computed torque control was carried out in order to minimize an error between target angles and real angles. The computed torque control is based on the equation of robot motion, which is derived from the Lagrange-Euler equation. To minimize the error between the real model and the approximated model, the adaptive control was carried out. During this simulation, the interference check was also carried out. The interference check verifies that the robot can move successfully without any collision.

디지털 오디오 코덱을 위한 새로운 비선형 역 양자화 알고리즘과 하드웨어 구조 (New Non-linear Inverse Quantization Algorithm and Hardware Architecture for Digital Audio Codecs)

  • 문종하;백재현;선우명훈
    • 한국통신학회논문지
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    • 제33권1C호
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    • pp.12-18
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    • 2008
  • 본 논문은 디지털 오디오 코덱에 효율적으로 적용 가능한 새로운 역 양자화 테이블 보간 알고리즘과 알고리즘에 특화된 DSP(Digital Signal Processor) 명령어 및 하드웨어 구조를 제안한다. 비선형 역 양자화 알고리즘은 대표적으로 MPEG-1 Layer-3와 MPEG-2/4 AAC(Advanced Audio Coding)에서 사용되며, 제안하는 명령어는 비선형 역 양자화에 최적화 되어 있다. 제안하는 알고리즘은 연산의 복잡도를 최소화하여 구현 시전체 연산량을 줄일 수 있으며, 제안된 알고리즘은 타 알고리즘에 비해 우수한 평균 오차값을 나타낸다. 제안하는 명령어 및 하드웨어 구조는 기존의 알고리즘과 비교하여 연산 과정에서 사용되는 명령어 수를 20% 정도 줄일 수 있으며, 역 양자화의 계산 부하를 효율적으로 줄일 수 있다. 제안한 알고리즘은 일반 상용 DSPEE 구현이 가능하다.

실시간 2차원 디지털 신호처리를 위한 VLSI 구조 (A VLSI Architecture for the Real-Time 2-D Digital Signal Processing)

  • 권희훈
    • 정보와 통신
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    • 제9권9호
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    • pp.72-85
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    • 1992
  • 다수의 처리 장치가 실시간 실현에 필수적이라는 것이 많은 디지털 신호처리를 일정한 시간 내에 하기 위한 요구 조건이다. VLSI 기술이 발전함으로 많은 기능 장치로 구성된 컴퓨터 시스템을 설계하고, 실현하는 것이 가능하게 되었다. 일정한 시간내에 높은 처리 능력을 갖음으로서 디지털 신호처리에 응용할 수 있는 VLSI 구조를 연구하는데 데이터 통신의 요구량과 계산의 복잡성을 최소화 할 수 있는 알고리듬의 개발이 요구된다. 이 문제를 해결하는 방법으로 DLSI 시스템이나 적응 시스템을 모델로 하는 효과적인 알고리듬을 조사하고 , 이 알고리듬을 실현할 수 있는 VLSI구조와 연관된 멀티 프로세서 시스템을 개발하는데 본 연구의 목적이 있다. 본 연구에서는 실시간 2차원 신호처리를 할 수 있는 새로운 VLSI 구조를 제안했다. 이 VLSI 구조는 칩 내부에서 단일 처리 장치가 갖는 개념을 다수의 처리 장치를 사용하는 경우로 확장하였다. 이 VLSI 구조는 입력 데이타의 크기가 증가함에 따라서 복잡성과 입력당 계산의 수가 증가하지 않는다는 장점을 갖기 때문에 매우 큰 2차원 데이타를 실시간에 처리할 수 있다.

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해상 상태 및 선저여유수심을 고려한 연안 내 선박의 최적 항로 결정 (Determination of Optimal Ship Route in Coastal Sea Considering Sea State and Under Keel Clearance)

  • 이원희;유원철;최광혁;함승호;김태완
    • 대한조선학회논문집
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    • 제56권6호
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    • pp.480-487
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    • 2019
  • Ship route planning is to find a route to minimize voyage time and/or fuel consumption in a given sea state. Unlike previous studies, this study proposes an optimization method for the route planning to avoid the grounding risk near the coast. The route waypoints were searched using A* algorithm, and the route simplification was performed to remove redundant waypoints using Douglas-Peucker algorithm. The optimization was performed to minimize fuel consumption by setting the optimization design parameters to the engine rpm. The sea state factors such as wind, wave, and current are also considered for route planning. We propose the constraint to avoid ground risk by using under keel clearance obtained from electoronic navigational chart. The proposed method was applied to find the optimal route between Mokpo and Jeju. The result showed that the proposed method suggests the optimal route that minimizes fuel consumption.

파이프라인 구조를 적용한 병렬 CRC 회로 설계 (Pipelined Parallel CRC)

  • 김기태;이현빈;박성주;박창원
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2005년도 추계종합학술대회
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    • pp.789-792
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    • 2005
  • In this paper, we propose a method that applies pipeline architecture to parallel CRC circuits. We developed a logic partitioning algorithm for applying pipeline architecture. Our algorithm can be used for the polynomial and the input data width, both of arbitrary length and minimize the logic level. Design experiments show the superiority of our approach in reducing the delay in comparison with previous works.

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