• ETRI Journal
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• v.25 no.6
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• pp.464-474
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• 2003

Component-based development leverages software reusability and reduces development costs. Enterprise JavaBeans (EJB) is a component model developed to reduce the complexity of software development and to facilitate reuse of components. However, EJB does not support component assembly by a plug-and-play technique due to the hard-wired composition at the code level. To cope with this problem, an architecture for EJB component assembly is defined at the abstract level and the inconsistency between the system architecture and its implementation must be eliminated at the implementation level. We propose a component-based application development tool named the COBALT assembler that supports the design and implementation of EJB component assembly by a plug-and-play technique based on the architecture style. The system architecture is first defined by the Architecture Description Language (ADL). The wrapper code and glue code are then generated for the assembly. After the consistency between the architecture and its implementation is checked, the assembled EJB components are deployed in an application server as a new composite component. We use the COBALT assembler for a shopping mall system and demonstrate that it can promote component reuse and leverage the system maintainability.

• Proceedings of the KAIS Fall Conference
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• 2003.11a
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• pp.50-56
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• 2003

In the development of complex software system, it is important to use hierarchical use case model due to the complex scope of development procedure. The use case model is core factor of the OMG (Object Management Group)'s UML (Unified Modeling Language) diagrams. In this paper, we propose a novel method to check syntactic consistency automatically in use case models at the different level of abstraction. This method is a rule-based approach which utilizes actor tree, use case tree and use case description. The proposed method is simulated on ITS (Intelligent Transportation System) architecture for the verification.

• Journal of KIISE:Software and Applications
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• v.30 no.9
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• pp.812-820
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• 2003

Component-Based Development(CBD) leverages software reusability and diminishes development costs. Various works about component models, such as EJB, COM, and CCM are in progress to support CBD. However, current component models hardly support flexible assembly of pre-built components. To cope with this problem, architecture for component assembly must be defined in the abstract level and the gap between system architecture and its implementation should be diminished in the implementation level. This paper proposes a method for architecture-based design and implementation of component assembly. Architecture is described by the ADL, and the tool, COBALT Assembler, is introduced to support the proposed design and implementation phase of component assembly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.73-84
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• 2004

This paper suggests a new scalar multiplication algerian to resist SPA which threatens the security of cryptographic primitive on the hardware recently, and discusses how to apply this algerian Our algorithm is better than other SPA countermeasure algorithms aspect to computational efficiency. Since known SPA countermeasure algorithms have dependency of computation. these are difficult to construct parallel architecture efficiently. To solve this problem our algorithm removes dependency and computes a multiplication and a squaring during inversion with parallel architecture in order to minimize loss of performance. We implement hardware logic with VHDL(VHSIC Hardware Description Language) to verify performance. Synthesis tool is Synplify Pro 7.0 and target chip is Xillinx VirtexE XCV2000EFGl156. Total equivalent gate is 60,508 and maximum frequency is 30Mhz. Our scalar multiplier can be applied to digital signature, encryption and decryption, key exchange, etc. It is applied to a embedded-micom it protects SPA and provides efficient computation.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.275-288
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• 2006

Rapid design space exploration is crucial to customizing embedded system design for exploiting the application behavior. As the time-to-market becomes a key concern of the design, the approach based on an application specific instruction-set processor (ASIP) is considered more seriously as one alternative design methodology. In this approach, the instruction set architecture (ISA) for a target processor is frequently modified to best fit the application with regard to code size and speed. Two goals of this paper is to introduce our new retargetable compiler and how it has been used in ASIP-based design space exploration for a popular digital signal processing (DSP) application. Newly developed retargetable compiler provides not only the functionality of previous retargetable compilers but also visualizes the features of the application program and profiles it so that it can help architecture designers and application programmers to insert new application specific instructions into target architecture for performance increase. Given an initial RISC-style ISA for the target processor, we characterized the application code and incrementally updated the ISA with more application specific instructions to give the compiler a better chance to optimize assembly code for the application. We get 32% performance increase and 20% program size reduction using 6 audio codec specific instructions from retargetable compiler. Our experimental results manifest a glimpse of evidence that a higgly retargetable compiler is essential to rapidly prototype a new ASIP for a specific application.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.62-64
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• 2006

With the advent of the international standard IEC 61850 for communication networks and systems in substations, utilities are beginning to implement substation automation systems (SAS) that can give support to interoperability, interchangeability and self-description features. This paper describes with the SAS design accordance with this new standard. After a brief introduction of IEC 61850 SCL, this paper addresses some issues related to the specification of an IEC 61850 based SAS, and describes the Substation Configuration Language (SCL) based on Extensible Markup Language (XML). The SAS design process is explored with examples including the Intelligent Electronic Device (IED) selection, Logical Nodes (LN) allocation and the related services and the SAS communication architecture.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11b
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• pp.448-450
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• 2005

Acme와 같은 ADL(Architecture Description Language) 들은 컴포넌트 기반 시스템의 아키텍쳐를 정형적으로 명세할 수 있는 장점을 가지고 있다. 하지만 날로 다각화되는 개발 과정 상의 이해관계들을 다 포용하지 못하고, 아키텍쳐에 특화된 별도의 표기 형식을 익혀야 하는 부담이 있어 아키텍쳐를 명세하는 언어로서 정착되지 못하고 있다. 반면 UML(Unified Modeling Language)은 범용 모델링 언어이여 소프트웨어 개발의 전 과정에 일관된 표기형식과 폭넓은 지원도구들을 제공하고 있어 소프트웨어 개발을 위한 사실상의 표준 언어로 자리잡고 있다. 이에 따라 지금까지 UML을 이용하여 아키텍쳐를 모델링하기 위한 연구들이 많이 진행되어 왔다. 특히 UML에서 표현수단이 미흡한 아키텍쳐의 핵심 개념들을 명시적으로 표현할 수 있도록 UML의 확장 메커니즘을 사용하여 UML을 특화하는 연구 결과들이 많이 소개되고 있으나 특화된 영역의 아키텍쳐를 기술하기에는 부족하다. 본 논문에서는 최근에 활발히 개발되고 있는 모바일 애플리케이션의 특징중의 하나인 device의 제약사항을 QoS로 정의하고 UML 확장메커니즘을 이용하여 모바일을 위한 아키텍쳐 모델링 언어 프레임웍을 제시하고 있다.

• ETRI Journal
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• v.27 no.5
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• pp.511-524
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• 2005

In this paper, we propose a novel hardware architecture for an intra-prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing $4{\times}4$ Hadamard transform and quantization during $16{\times}16$ prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix $0.35 {\mu}m$ TLM (triple layer metal) library.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1149-1152
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• 1998

멀티미디어 데이터를 아날로그 방식보다는 디지털 방식으로 처리하게 되면 여러 면에서 이득을 볼 수 있다. 멀티미디어 데이터를 디지털 방식으로 처리하는 방법 중 범용프로세서에서 멀티미디어 명령어에 의해 처리하게 되면 flexibility를 증가시키며 효율적으로 프로그램할 수 있다. 본 논문에서는 범용 프로세서 안에서 멀티미디어 데이터를 효율적으로 처리할 수 있는 명령어 집합 구조와 이를 수행할 수 있는 프로세서의 구조를 제안하고 이를 HDL(Hardware Description Language)로 동작레벨에서 기술하고 시뮬레이션 하였다. 제안된 멀티미디어 명령어는 특성에 따라 8개의 그룹에 총 55개의 명령어로 구성되며 64비트 데이터 안에서 각각 8비트의 8바이트, 16비트의 4하프워드, 32비트의 2워드의 부워드(subword) 데이터들을 병렬 처리한다. 모델링된 프로세서는 오픈아키텍쳐(Open Architecture)인 SPARC V.9 의 정수연산장치(Integer Unit)에 기반을 두었으며 하바드 구조를 지닌 5단 파이프라인 RISC 형태이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1939-1947
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• 2000

본 논문에서는 명령어의 효율적인 페치를 위해 분기 타겟 주소 전체를 사용하지 않고 캐쉬 메모리(cache memory) 내의 적은 비트 수로 인덱싱 하여 한 클럭 사이클 안에 최대 4개의 명령어를 다음 파이프라인으로 보내줄 수 있는 방법을 제시한다. 본 프리페치 유닛은 크게 나누어 3개의 영역으로 나눌 수 있는데, 분기에 관련하여 미리 부분적으로 명령어를 디코드 하는 프리디코드(predecode) 블록, 타겟 주소(NTA : Next Target Address) 테이블 영역을 추가시킨 명령어 캐쉬(instruction cache) 블록, 전체 유닛을 제어하고 가상 주소를 관리하는 프리페치(prefetch) 블록으로 나누어진다. 사용된 명령어들은 SPARC(Scalable Processor ARChitecture) V9에 기준 하였고 구현은 Verilog-HDL(Hardwave Description Language)을 사용하여 기능 수준으로 기술되고 검증되었다. 구현된 프리페치 유닛은 명령어 흐름에 분기가 존재하더라도 단일 사이클 안에 4개까지의 명령어들을 정확한 예측 하에 다음 파이프라인으로 보내줄 수 있다. 또한 NTA를 사용한 방법은 같은 수의 레지스터 비트를 사용하였을 때 BTB(Branch Target Buffer)를 사용하는 방법과 비교하여 2배정도 많은 개수의 분기 명령 주소를 저장할 수 있는 장점이 있다.