• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.12
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• pp.4617-4632
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• 2021

IEEE 802.11ax is a protocol being developed for high-density Wireless Local Area Networks (WLAN). Several algorithms have been proposed to improve the level of spatial reuse applied in IEEE 802.11ax. However, these algorithms are tentative and do not specify how to select the transmit power and carrier sense threshold in practice; It is unclear when and why the tuned parameters lead to better network performance. In this paper, we restricted the scale of transmit power tuning to prevent the case of backfire in which spatial reuse will result in transmission failure. If the restrictions cannot be satisfied, spatial reuse will be abandoned. This is why we named the proposed scheme as Arbitration based Spatial Reuse (ASR). We quantified the network performance after spatial reuse, and formulate a corresponding maximum problem whose solution is the optimal carrier sense threshold and transmit power. We verified our theoretical analysis by simulation and compared it with previous studies, and the results show that ASR improves the throughput up to 8.6% compared with 802.11ax. ASR can avoid failure of spatial reuse, while the spatial reuse failure rate of existing schemes can up to 36%. To use the ASR scheme in practice, we investigate the relation between the optimal carrier sense threshold and transmit power. Based on the relations got from ASR, the proposed Relation based Spatial Reuse (RSR) scheme can get a satisfactory performance by using only the interference perceived and the previously found relations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1184-1195
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• 1998

In this paper, we compare vaious input-buffered ATM switch architectures in structures on input buffer and switching fabric, the resons for performance improvement and degradation, arbitration scheme and maximum throughput, and present comparative merits and demerits of each architecture under random and bursty traffic. We also analyze the prformance of combined architectures of windowing scheme, destination-queueing based input-port expansion schemeand output-port expansion scheme, and show that it is possible to achieve 100% throughput with combined scheme of destination-queueing based input-port expansion scheme and output-port expansio scheme when the number of output group is 2 and output port expansion ratio is 2.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.10
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• pp.3458-3474
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• 2014

The performance of IEEE 802.11e enhanced distributed channel access (EDCA) is influenced by several interactive parameters that make quality of service (QoS) control complex and difficult. In EDCA, the most critical performance influencing parameters are the arbitration interframe space (AIFS) and contention window size (CW) of each access category (AC). The objective of this paper is to provide a scheme for parameter control such that the throughput per station as well as the overall system throughput of the network is maximized and controllable. For this purpose, a simple and accurate analytical model describing the throughput behavior of EDCA networks is presented in this paper. Based on this model, the paper further provides a scheme in which a Pareto optimal system configuration is obtained via an appropriate CW control for a given AIFS value, which is a different approach compared to relevant papers in the literature that deal with CW control only. The simulation results confirm the effectiveness of the proposed method which shows significant performance improvements compared to other existing algorithms.

• Journal of Arbitration Studies
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• v.16 no.3
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• pp.161-189
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• 2006

This paper is aiming at analyzing case law of India in relation with reasonable time to make decision whether to accept or to refuse the documents received from the presenter in credit transactions. As specified in UCP, the failure to refuse to accept the documents within a reasonable time precludes the Issuing Bank, Confirming Bank (if any) and Nominated Bank from asserting that they are discrepant. Compliance of the stipulated documents on their face with the terms and conditions of the credit shall be determined by international standard banking practice as reflected in this Articles of UCP 500. The Issuing bank is only to be held responsible for honoring the documents presented by beneficiary through the nominated banks if they are strictly in compliance with terms and conditions of the Credit. As any well experienced banker knows, however, a word-by-word, letter-by-letter correspondence between the documents and the credit terms means a practical impossibility. Thus the notion of reasonable care in conjunction with the doctrine of strict compliance mixed with International Standard Banking Practices has not played a right functional standard for checking the documents as stipulated in the credit and UCP 500. And so the rejection rate is highly estimated at approximately 50% in EU and 40 to 70% according to their geographical locations in the USA. As a result, it can possibly be inferred from this fact that the credit industry would be facing the functional failure as the international trade credit facility, if not supported with motive power as a relevant scheme in UCP 500. It is quite important to note that UCP 500 Article 13(b) which specify the time limit for the banks to notify the presenter their decision not to accept the documents within a reasonable time not to exceed seven banking days following the day of receipt of documents would be the motive engine to improve the negotiability of documents in international trade financial facility.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.8 no.3
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• pp.132-137
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• 2009

In this paper, a position recognition system is designed, implemented, and tested using IEEE 802.15.4a PHY (CSS) hardware and Tiny OS environment. The system is designed with extensibility and flexibility. The system consists of five kinds of nodes which have different functions from each other. Three communication channels are used for collision avoidance. In each cell, an arbiter node is used to minimize message collisions. The proposed arbitration protocol is designed to support mobility of arbitrary target nodes. Target nodes calculates their locations with communications to four location reference nodes which are placed on the comers of each cell.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10a
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• pp.770-775
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• 1987

In this paper, design and development experiences of a vision based robotic assembly system for electronic components are described. Specifically, the overall system consists of the following three subsystems each of which employs a 16 bit Preprocessor MC 68000 : supervisory controller, real-time vision system, and servo system. The three microprocessors are interconnected using the time shared common memory bus structure with hardwired bus arbitration scheme and operated as a master-slave type in which each slave is functionally fixed in view of software. With this system architecture, the followings are developed and implemented in this research; (i) the system programming language, called 'CLRC', for man-machine interface including the robot motion and vision primitives, (ii) real-time vision system using hardwired chain coder, (iii) the high-precision servo techniques for high speed de motors and high speed stepping motors. The proposed control system were implemented and tested in real-time successfully.

• ETRI Journal
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• v.28 no.3
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• pp.397-400
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• 2006

The multi-layer advanced high-performance bus (ML-AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML-AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML-AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML-AHB BusMatrix of an ADK with the elimination of the heavy input stages.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1401-1411
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• 1999

Due to the increase of multimedia services, multicasting is considered as important design factor for ATM switch. To resolve the traffic expansion problem that is occurred by multicast in multistage interconnection networks, this paper proposes the multicast switch using a high-speed bus and a shared memory switch. Since the proposed switch uses a high-speed time division bus as a connection medium and chooses a shared memory switch as a basic switch module, it provides good port scalability. The traffic arbitration scheme enables internal non-blocking. By simulation we proves a good performance in the data throughput and the cell delay.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.793-796
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• 2007

RFID (Radio Frequency IDentification) 리더의 동작 영역은 리더의 감도와 전력이 도달할 수 있는 거리에 의해 제한된다. RFID Shower 는 근접한 리더로부터 전송되는 신호를 증폭하여 리더의 동작영역을 확장한다. 그러나, RFID Shower 의 동작 영역 안에 여러 리더들이 있을 경우 리더들간의 신호충돌이 발생한다. 이를 해결하기 위해 중재 알고리즘이 제안되었다. 본 논문에서는 RFID 리더들을 위한 중재 알고리즘을 DEVS 형식론에 기반하여 모델링하고 시뮬레이션 하여 성능을 측정, 비교하였다.